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SLG46169 Datasheet(PDF) 37 Page - Dialog Semiconductor

No. de pieza SLG46169
Descripción Electrónicos  GreenPAK Programmable Mixed-signal Matrix
Download  102 Pages
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Fabricante Electrónico  DIALOG [Dialog Semiconductor]
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SLG46169 Datasheet(HTML) 37 Page - Dialog Semiconductor

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SLG46169
reg<233:228>
Matrix Out: In0 of LUT3_1
38
reg<239:234>
Matrix Out: In1 of LUT3_1
39
reg<245:240>
Matrix Out: In2 of LUT3_1
40
reg<251:246>
Matrix Out: In0 of LUT3_2 or Clock Input of DFF2
41
reg<257:252>
Matrix Out: In1 of LUT3_2 or Data Input of DFF2
42
reg<263:258>
Matrix Out: In2 of LUT3_2 or nRST (nSET) Input of DFF2
43
reg<269:264>
Matrix Out: In0 of LUT3_3 or Clock Input of DFF3
44
reg<275:270>
Matrix Out: In1 of LUT3_3 or Data Input of DFF3
45
reg<281:276>
Matrix Out: In2 of LUT3_3 or nRST (nSET) of DFF3
46
reg<287:282>
Matrix Out: In0 of LUT3_4
47
reg<293:288>
Matrix Out: In1 of LUT3_4
48
reg<299:294>
Matrix Out: In2 of LUT3_4
49
reg<305:300>
Matrix Out: In0 of LUT3_5
50
reg<311:306>
Matrix Out: In1 of LUT3_5
51
reg<317:312>
Matrix Out: In2 of LUT3_5
52
reg<323:318>
Matrix Out: In0 of LUT3_6
53
reg<329:324>
Matrix Out: In1 of LUT3_6
54
reg<335:330>
Matrix Out: In2 of LUT3_6
55
reg<341:336>
Matrix Out: In0 of LUT3_7
56
reg<347:342>
Matrix Out: In1 of LUT3_7
57
reg<353:348>
Matrix Out: In2 of LUT3_7
58
reg<359:354>
Matrix Out: In0 of LUT3_8 or Input of Pipe Delay
59
reg<365:360>
Matrix Out: In1 of LUT3_8 or nRST of Pipe Delay
60
reg<371:366>
Matrix Out: In2 of LUT3_8 or Clock of Pipe Delay
61
reg<377:372>
Matrix Out: In0 of LUT2_0 or Clock Input of DFF4
62
reg<383:378>
Matrix Out: In1 of LUT2_0 or Data Input of DFF4
63
reg<389:384>
Matrix Out: In0 of LUT2_1 or Clock Input of DFF5
64
reg<395:390>
Matrix Out: In1 of LUT2_1 or Data Input of DFF5
65
reg<401:396>
Matrix Out: In0 of LUT2_2 or Clock Input of DFF6
66
reg<407:402>
Matrix Out: In1 of LUT2_2 or Data Input of DFF6
67
reg<413:408>
Matrix Out: In0 of LUT2_3 or Clock Input of DFF7
68
reg<419:414>
Matrix Out: In1 of LUT2_3 or Data Input of DFF7
69
reg<425:420>
Matrix Out: In0 of LUT2_4
70
reg<431:426>
Matrix Out: In1 of LUT2_4
71
reg<437:432>
Matrix Out: In0 of LUT2_5
72
reg<443:438>
Matrix Out: In1 of LUT2_5
73
reg<449:444>
Matrix Out: Input for Programmable Delay & Edge Detector
74
reg<455:450>
Matrix Out: Power Down for Osc
75
reg<461:456>
Reserved
76
Table 25. Matrix Output Table
Register Bit
Address
Matrix Output Signal Function
Matrix Output
Number


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