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SLG46200 Datasheet(PDF) 20 Page - Dialog Semiconductor |
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SLG46200 Datasheet(HTML) 20 Page - Dialog Semiconductor |
20 / 69 page 000-0046200-124 Page 15 of 64 SLG46200 8.4 DCMP1 Functional Diagram 8.5 DCMP0 & DCMP1 Register Settings Figure 4. DCMP1 Functional Diagram Table 7. DCMP0 & DCMP1 Register Settings Signal Function Register Bit Address Register Definition DCMP IN- Selection Control <318> 0: reg<400:399> for DCMP0, reg<404:403> for DCMP1 1: from Connection Matrix Out <11:10> DCMP IN- Input Signal <382:375> 00000000 to 11111111: User defined 8-bit signal input Register0 for DCMP0 and Register2 for DCMP1 DCMP IN- Input Signal <390:383> 00000000 to 11111111: User defined 8-bit signal input Register1 for DCMP0 and Register0 for DCMP1 DCMP IN- Input Signal <398:391> 00000000 to 11111111: User defined 8-bit signal input Register2 for DCMP0 and Register1 for DCMP1 DCMP0 IN- Input Selection from reg<318> <400:399> 00: From S2P<15:8> 01: From reg<382:375> 10: From reg<390:383> 11: From reg<398:391> DCMP0 IN+ Input Selection <401> 0: From S2P<7:0> 1: From ADC Output DCMP0 & DCMP1 Power Down <402> 0: Power down mode 1: Power on mode DCMP1 IN- Input Selection from reg<318> <404:403> 00: From S2P<7:0> 01: From reg<390:383> 10: From reg<398:391> 11: From reg<382:375> DCMP1 IN+ Input Selection <405> 0: From S2P<15:8> 1: From ADC Output 1 0 S2P <15:8> reg <405> ADC 8-bit comparator IN- IN+ 01 00 S2P <7:0> reg <382:375> 11 10 reg <390:383> reg <398:391> 1 0 reg <404:403> Connection Matrix output <11:10> reg <318> To Connection Matrix input <24> To Connection Matrix input <26> EQ OUT in ip DCMP1 reg <402> Power On Select 0 = Power Down 1=PowerOn To PWM in <3> in_out <1:0> 8 8 2 MTRX SEL#<1:0> CLK4PWM |
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