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SLG46532 Datasheet(PDF) 59 Page - Dialog Semiconductor

No. de pieza SLG46532
Descripción Electrónicos  GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine and Dual Supply
Download  184 Pages
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Fabricante Electrónico  DIALOG [Dialog Semiconductor]
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SLG46532 Datasheet(HTML) 59 Page - Dialog Semiconductor

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SLG46532
reg <311:304>
Matrix OUT: PIN13 Digital Output Source
38
reg <319:312>
Matrix OUT: PIN13 Output Enable
39
reg <327:320>
Matrix OUT: Inverter Input
40
reg <335:328>
Reserved
41
reg <343:336>
Matrix OUT: PIN15 Digital Output Source
42
reg <351:344>
Matrix OUT: PIN16 Digital Output Source
43
reg <359:352>
Matrix OUT: PIN16 Output Enable
44
reg <367:360>
Matrix OUT: PIN17 Digital Output Source
45
reg <375:368>
Matrix OUT: PIN18 Digital Output Source
46
reg <383:376>
Matrix OUT: PIN18 Output Enable
47
reg <391:384>
Matrix OUT: PIN19 Digital Output Source
48
reg <399:392>
Matrix OUT: PIN19 Output Enable
49
reg <407:400>
Matrix OUT: PIN20 Digital Output Source
50
reg <415:408>
Matrix OUT: ACMP0 PDB (Power Down)
51
reg <423:416>
Matrix OUT: ACMP1 PDB (Power Down)
52
reg <431:424>
Matrix OUT: ACMP2 PDB (Power Down)
53
reg <439:432>
Matrix OUT: ACMP3 PDB (Power Down)
54
reg <447:440>
Matrix OUT: Input of Filter_0 with fixed time edge detector
55
reg <455:448>
Matrix OUT: Input of Filter_1 with fixed time edge detector
56
reg <463:456>
Matrix OUT: Input of Programmable Delay & Edge Detector
57
reg <471:464>
Matrix OUT: OSC 25KHz/2MHz PDB (Power Down)
58
reg <479:472>
Matrix OUT: OSC 25MHz PDB (Power Down)
59
reg <487:480>
Matrix OUT: IN0 of LUT2_0 or Clock Input of DFF0
60
reg <495:488>
Matrix OUT: IN1 of LUT2_0 or Data Input of DFF0
61
reg <503:496>
Matrix OUT: IN0 of LUT2_1 or Clock Input of DFF1
62
reg <511:504>
Matrix OUT: IN1 of LUT2_1 or Data Input of DFF1
63
reg <519:512>
Matrix OUT: IN0 of LUT2_2 or Clock Input of DFF2
64
reg <527:520>
Matrix OUT: IN1 of LUT2_2 or Data Input of DFF2
65
reg <535:528>
Matrix OUT: IN0 of LUT2_3 or Clock Input of PGEN
66
reg <543:536>
Matrix OUT: IN1 of LUT2_3 or nRST of PGEN
67
reg <551:544>
Matrix OUT: IN0 of LUT3_0 or Clock Input of DFF3
68
reg <559:552>
Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3
69
reg <567:560>
Matrix OUT: IN2 of LUT3_0 or nRST (nSET) of DFF3
70
reg <575:568>
Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4
71
reg <583:576>
Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4
72
reg <591:584>
Matrix OUT: IN2 of LUT3_1 or nRST (nSET) of DFF4
73
reg <599:592>
Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5
74
reg <607:600>
Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5
75
reg <615:608>
Matrix OUT: IN2 of LUT3_2 or nRST (nSET) of DFF5
76
Table 42. Matrix Output Table
Register Bit
Address
Matrix Output Signal Function
Note: For each Address, the two most significant bits are unused)
Matrix Output
Number


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