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TSB14AA1A Datasheet(PDF) 10 Page - Texas Instruments |
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TSB14AA1A Datasheet(HTML) 10 Page - Texas Instruments |
10 / 37 page 1–5 1.5 Terminal Descriptions (Continued) TERMINAL TYPE I/O DESCRIPTION NAME NO. TYPE I/O DESCRIPTION LPS 1 CMOS I Link power status input. This pin monitors the active/power status of the link layer controller and controls the state of the PHY-LLC interface. This pin must be connected to either a pulsed output that is active when the LLC is powered, or to the VDD supplying the LLC through a 10-kΩ resistor. The LPS input is considered inactive if it is sampled low by the PHY for more than 128 SCLK cycles and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to ensure observation as high by the PHY. When the TSB14AA1A detects that LPS is inactive, it will place the PHY-LLC interface into a low–power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SCLK output remains active. If the LPS input remains low for more than 1280 SCLK cycles, the PHY-LLC interface is placed into a low-power disabled state in which the SCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if the LPS input is active. LREQ 3 CMOS I Link request input. The LLC uses this input to initiate a service request to the TSB14AA1A. M-TEST 26 CMOS I Manufacturing tests. When M-TEST is set high, manufacturing test modes are enabled. For normal operation, this pin must be set low. OCDOE 25 CMOS O Open collector driver output enable pin. This pin is driven low to enable the open-collector transceivers for both TDATA and TSTRB. OCDOE is also used to enable the TSTRB transceiver when used with 3-state transceivers. When IDS is high, the output of this pin is inverted. PD 37 CMOS I Power-down input. This pin is used for manufacturing tests. It should be tied to ground for normal operation. RDATA 35 TTL I Receive data input. Incoming data from the external transceiver is received at the data rate set by the CLK_SELX pins and input clock frequency. When IDS is high the pin input is inverted. RESET 48 CMOS I Hardware reset input. When pulsed low for a minimum of (2*SCLK) seconds, a hardware reset is initiated. RSTRB 33 TTL I Receive strobe input. The incoming strobe signal from the external transceiver is received at the data rate set by the CLK_SELX pins and input clock frequency. When IDS is high the pin input is inverted. SCAN_EN 11 CMOS I Scan enable. When set high this pin enables the manufacturing scan test of the TSB14AA1A device. It is set low for normal operation. SCLK 5 CMOS O System clock output. This pin provides a clock signal synchronized with the data transfers and output to the link. It pulses at a rate of 1/2 the data rate. At a data rate of 98.304 Mbps it oscillates at 49.152 MHz, and at a data rate of 49.152 Mbps it oscillates at 24.576 MHz. T1P8 39 O 1.8 V regulator output. This pin is the output of the on-chip 1.8 V voltage regulator. T1P8 must be decoupled to GND with a 0.1 µF capacitor. TDATA 29 CMOS O Transmit data output. Data to be transmitted is serialized on TDATA and output to the external transceiver. When IDS is high the pin output is inverted. TDOE 31 CMOS O 3-state (high-impedance) driver output enable. This pin will only be asserted under any of the following conditions: 1. Data is transmitted after winning arbitration. 2. The arbitration state being driven is 1 (TDATA and TSTRB both = 1). 3. Bus reset is initiated. It is driven low to enable high impedance transceivers for the TDATA signal. When IDS is high the pin output is inverted. TEST_EN 36 CMOS I Test enable input. When set high, this pin enables a manufacturing test mode. In normal operation, this pin must be tied to GND. TSTRB 27 CMOS O Transmit strobe output. TSTRB encodes the transmit of the strobe signal and the output to the external transceiver. When IDS is high the pin output is inverted. VCC 6, 17, 30, 42 Supply I 3.3-V supply voltage Xl 43 Crystal I Crystal oscillator input. When used with an oscillator, this pin must be connected to the output of the oscillator. When operating at 98.304 Mbps this input must be 98.304 MHz. When operating at 49.152 Mbps, this input must be 49.152 MHz. XO 45 Crystal O Oscillator output. When used with an oscillator, this pin must be left unconnected. |
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