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ADC102S101 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
No. de pieza ADC102S101
Descripción Electrónicos  2 Channel, 1 MSPS 12-Bit A/D Converter
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC102S101 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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ADC122S101 Timing Specifications
The following specifications apply for V
A = +2.7V to 5.25V, GND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1
MSPS, C
L =35pF, Boldface limits apply for TA =TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
t
CSU
Setup Time SCLK High to CS Falling Edge
(Note 10)
V
A = +3.0V
−3.5
10
ns (min)
V
A = +5.0V
−0.5
t
CLH
Hold time SCLK Low to CS Falling Edge
(Note 10)
V
A = +3.0V
+4.5
10
ns (min)
V
A = +5.0V
+1.5
t
EN
Delay from CS Until DOUT active
V
A = +3.0V
+4
30
ns (max)
V
A = +5.0V
+2
t
ACC
Data Access Time after SCLK Falling Edge
V
A = +3.0V
+14.5
30
ns (max)
V
A = +5.0V
+13
t
SU
Data Setup Time Prior to SCLK Rising Edge
+3
10
ns (min)
t
H
Data Valid SCLK Hold Time
+3
10
ns (min)
t
CH
SCLK High Pulse Width
0.5 x
t
SCLK
0.3 x
t
SCLK
ns (min)
t
CL
SCLK Low Pulse Width
0.5 x
t
SCLK
0.3 x
t
SCLK
ns (min)
t
DIS
CS Rising Edge to DOUT High-Impedance
Output Falling
V
A = +3.0V
1.8
20
ns (max)
V
A = +5.0V
1.3
Output Rising
V
A = +3.0V
1.0
V
A = +5.0V
1.0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (
θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k
Ω resistor. Machine model is 220 pF discharged through zero ohms.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by tCSU and tCLH.
www.national.com
5


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