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SI9978DW-T1-E3 Datasheet(PDF) 4 Page - Vishay Siliconix

No. de pieza SI9978DW-T1-E3
Descripción Electrónicos  Configurable H-Bridge Driver
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Fabricante Electrónico  VISHAY [Vishay Siliconix]
Página de inicio  http://www.vishay.com
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SI9978DW-T1-E3 Datasheet(HTML) 4 Page - Vishay Siliconix

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background image
VDD
V+
EN/ENA
CAPA
DIR/INA
SA
PWM/ENB
21
GTA
QS/INB
MODE
BRK
GBA
CAPB
SB
CL/FAULTB
GTB
FAULT/FAULTA
GBB
NC
GND
RA/CA
ILB+
RB/CB
ILA+
SO-24
(Wide Body)
22
23
24
2
3
4
1
18
19
20
5
6
7
17
8
14
15
16
9
10
11
13
12
Top View
Si9978
Vishay Siliconix
www.vishay.com
4
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
PIN CONFIGURATION AND ORDERING INFORMATION
ORDERING INFORMATION
Part Number
Lead (Pb)-Free
Part Number
Temperature
Range
Package
Si9978DW
40 to 85_C
SOIC-24
Si9978DW-T1
Si9978DW-T1—E3
−40 to 85_C
SOIC-24
(Wide Body)
PIN DESCRIPTION
Pin 1: VDD
VDD is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 mF is recommended.
Pin 2: EN/ENA
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 3: DIR/INA
The function of this pin is determined by the MODE pin. When
the MODE pin is at logic “1”, it is the DIR pin, and when MODE
is at logic “0”, it is the INA pin.
As the DIR input, it is the direction control for the H-bridge, and
determines which diagonal pair of power MOSFETs is active.
A logic “1” turns on GTA and enables GBB, while a logic “0”
turns on GTB and enables GBA. When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
As the INA pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
Pin 4: PWM/ENB
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a logic
“1”. When the mode pin is at logic “0”, this pin becomes the
ENABLE pin for half-bridge B.
Pin 5: QS/INB
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1” on
this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned on,
and when at logic “0”, the low-side MOSFET is turned on.


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