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SN74GTLP2033DGGR Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza SN74GTLP2033DGGR
Descripción Electrónicos  8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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SN74GTLP2033DGGR Datasheet(HTML) 1 Page - Texas Instruments

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SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
D LVTTL Interfaces Are 5-V Tolerant
D High-Drive GTLP Open-Drain Outputs
(100 mA)
D LVTTL Outputs (–24 mA/24 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides
a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP’s reduced output swing (
<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
 circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11
Ω.
Copyright
 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
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IMODE1
AI1
AO1
GND
AI2
AO2
VCC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
VCC
AO7
AI7
GND
AO8
AI8
OMODE0
IMODE0
BIAS VCC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
VCC
B7
LOOPBACK
GND
B8
VREF
OMODE1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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