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LTM4633 Datasheet(PDF) 17 Page - Linear Technology

No. de pieza LTM4633
Descripción Electrónicos  Triple 10A Step-DownDC/DC 關Module Regulator
Download  32 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTM4633 Datasheet(HTML) 17 Page - Linear Technology

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LTM4633
17
4633f
For more information www.linear.com/LTM4633
applicaTions inForMaTion
ensure the voltage at CNTL_PWR is always greater than
the voltage at EXTVCCatalltimesincludingduringstart-up
and shutdown. Connecting VOUT3 to EXTVCC may present
a convenient way to meet the sequencing requirement if
VOUT3 is a 5V output. Otherwise float EXTVCC if not used.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD 51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD 51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers in lieu or to compliment any FEA activities
may opt to use laboratory equipment and a test vehicle
such as the demo board to anticipate the µModule regula-
tor’s thermal performance in their application at various
electricalandenvironmentaloperatingconditions.Without
FEA software, the thermal resistances reported in the Pin
Configurationsectionarein-and-ofthemselvesnotrelevant
toprovidingguidanceofthermalperformance;instead,the
deratingcurvesprovidedlaterinthedatasheetcanbeused
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section provides values based on
four thermal coefficients explicitly defined in JESD 51-12;
these coefficients are quoted or paraphrased:
1.
θJA:Thethermalresistancefromjunctiontoambient,is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move.Thisvalueisdeterminedwiththepartmountedto
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2.
θJCbottom: The thermal resistance from the junction to
the bottom of the product case, is determined with all
of the internal power dissipation flowing through the
bottom of the package. In a typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3.
θJCtop: The thermal resistance from junction to top of
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of
θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4.
θJB: The thermal resistance from junction to the printed
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
of the µModule package and into the board, and is really
the sum of the
θJCbottom and the thermal resistance of
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured at a specified distance from the package,
using a 2-sided, 2-layer board. This board is described
in JESD 51-9.


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