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LTM4636-1 Datasheet(PDF) 9 Page - Linear Technology |
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LTM4636-1 Datasheet(HTML) 9 Page - Linear Technology |
9 / 38 page LTM4636-1 9 46361fa For more information www.linear.com/LTM4636-1 PIN FUNCTIONS HIZREG (F3): When this pin is pulled low the power stage is disabled into high impedance. Tie this pin to VIN or INTVCC for normal operation. OVER_TEMP (D10): This overtemperature protection is programmable with an internal monitor that is referenced to the TMON pin and the OTP_SET pin. The OVER_TEMP pin can be used to alert the system if the module regulator overheats, and this signal can be used to trip off and retry an electronic circuit breaker in a fault condition. The pin is an open collector that pulls active low in response to OVER_TEMP.TheOVER_TEMPpincanbeleftfloatingifnot used. See the Applications Information section for details. SGND(F4,G4):SignalGroundPin.Returngroundpathfor all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 18. INTVCC (F6): Internal 5.5V LDO for Driving the Control Circuitry in the LTM4636-1. INTVCC is controlled and enabled when RUNC is activated high. FREQ (G5): A resistor can be applied from this pin to ground to set the operating frequency. This pin sources 20µA. See the Applications Information section. PHMODE (G7): This pin can be voltage programmed to changethephaserelationshipoftheCLKOUTpinwithrefer- ence to the internal clock or an input synchronized clock. The INTVCC (5.5V) output can be voltage divided down to the PHASMD pin to set the particular phase. The Electri- cal Characteristics show the different settings to select a particularphase.SeetheApplicationsInformationsection. RUNP (G8): This pin enables the PVCC supply. This pin can be connected to VIN, or tie to ground when connecting PVCC to VIN ≤ 5.5V. RUNP needs to sequence up before RUNC. A 15k resistor from PVCC to RUNC with a 0.1µF capacitor will provide enough delay. In parallel operation with multiple LTM4636-1s, the resistor can be reduced in value by N times and the 0.1µF can be increased N times. SeeApplicationsInformationsection.RUNPcanbeusedto set the minimum UVLO with a voltage divider. See Figure 1. PVCC (F9): 5V Power Output and Power for Internal Power MOSFETDrivers.Theregulatorcanpower50mAofexternal sourcing for additional use. Place a 22µF ceramic filter capacitor on this pin to ground. When VIN < 5.5V, tie VIN and PVCC together. Then tie RUNP to GND. If VIN > 5.5V then operate PVCC regulator as normal. See the Typical Application examples. OVP_SET (E12): This pin is used to set the output overvolt- agetrippoint.Thispinhasa24.9kΩresistoronittoground. See the Applications Information section. Float is not used. BIAS (G9): This pin is used to power the OTP and OVP circuitry independently of the main power feed. See the Applications Information section. TEMP+ (G12): Temperature Monitor. An internal diode connected NPN transistor. See the Applications Informa- tion section. OTP_SET(F11):Thispinisusedtosettheovertemperature set point. The pin has a 24.9k resistor on it to ground. See Applications Information section. Float if not used. TEMP– (G11): Low Side of the Internal Temperature Monitor. CLKOUT (G3): Clock out signal that can be phase selected to the main internal clock or synchronized clock using the PHASMD pin. CLKOUT can be used for multiphase applications. See the Applications Information section. TEST1 (H4), TEST2 (F5), TEST3 (H2), GMON (H9):These are test pins used in the final production test of the part. Leave floating. VIN (H5-H6, J4-J7, K4-K8, L4-L8, M4-M8): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN and GND pins. PWM(H7):PWMoutputthatdrivesthepowerstage.Primar- ily used for test, but can be monitored in debug or testing. TMON(H8):TemperatureMonitorPin.Internaltemperature monitor,variesfrom1.0Vat25°Cto1.44Vat150°C,disables power stage at >150°C. The OTP_Trip signal is set to trip off at a value lower than 150°C. If the temperature moni- tor feature is not desired, then tie the TMON pin to GND. SW (L11, K11): These are pin connections to the internal switch node for test evaluation and monitoring. An R-C snubber can be placed from the switch pins to GND to eliminate any high frequency ringing. See the Applications Information section. |
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