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AK4132 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AK4132 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 27 page [AK4132] 015015036-E-03 2018/05 - 4 - ■ Pin Functions No. Pin Name I/O Function PDN= “L” Status 1 ODIF I Audio Interface Format Select Pin for Output PORT - 2 IDIF I Audio Interface Format Select Pin for Input PORT - 3 CM I Output Port Mode Select Pin “H”: Slave Mode “L”: Master Mode - 4 TEST I Test pin. Must be connected to DVSS in normal use. It has a pull-down resister 100k . - 5 ILRCK I Channel Clock Input Pin for Input PORT - 6 IBICK I Audio Serial Clock Input Pin for Input PORT - 7 SDTI I Audio Serial Data Input Pin for Input PORT - 8 OMCLK I External Master Clock Input - 9 OLRCK O Channel Clock Output Pin for Output PORT in Master Mode “L” I Channel Clock Input Pin for Output PORT in Slave Mode - 10 OBICK O Audio Serial Clock Output Pin for Output PORT in Master Mode “L” I Audio Serial Clock Input Pin for Output PORT in Slave Mode - 11 SDTO O Audio Serial Data Output Pin for Output PORT “L” 12 VD18 I Internal Digital Power Supply Pin, 1.7 1.9V (VSEL= “H”) - O Regulator Output Pin, Typ. 1.8V (VSEL= “L”) Current must not be taken from this pin. A 10μF (±30%; including the temperature characteristics) capacitor should be connected between this pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. “L” 13 DVSS - Digital Ground Pin - 14 DVDD - Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V - 15 VSEL I Internal Digital Power Supply Select Pin “H”: External Power Supply “L”: Internal Regulator - 16 PDN I Power-Down Mode Pin “H”: Power Up “L”: Power Down and Reset The AK4132 should be reset once by bringing PDN pin = “L” upon power-up. - Note 1. All input pins should not be allowed to float. Note 2. CM, ODIF and IDIF must be changed when the PDN pin = “L”. ■ Handling of Unused Pin Classification Pin Name Setting Digital OMCLK Connect to DVSS |
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