SD1210 datasheet(6/46 Pages) ETC

No. de pieza	SD1210

Descripción Electrónicos	Dual-Interface SXGA TFT LCD Display Controller

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Fabricante Electrónico	ETC [List of Unclassifed Manufacturers]

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SmartASIC, Inc.

SD1210

November, 1999

SmartASIC Confidential

6

Revision B

Table 1: SD1210 pin description (sorted by pin number)

Symbol

PIN Number

I/O

Description

B_IN10

1

I

Channel B Data Input Color Blue (LSB)

B_IN11

2

I

Channel B Data Input Color Blue

B_IN12

3

I

Channel B Data Input Color Blue

B_IN13

4

I

Channel B Data Input Color Blue

DATA_SEL

5

I

Indicate Channel A or Channel B contains valid input

data:

1: data in Channel A is valid

0: data in Channel B is valid

B_IN14

6

I

Channel B Data Input Color Blue

B_IN15

7

I

Channel B Data Input Color Blue

B_IN16

8

I

Channel B Data Input Color Blue

B_IN17

9

I

Channel B Data Input Color Blue (MSB)

ROM_SCL

10

O

SCL in I

2C for EEPROM interface

ROM_SDA

11

I/O

SDA in I

2C for EEPROM interface

GND

12

Ground

CPU_SCL

13

I

SCL in I

2C for CPU interface

CPU_SDA

14

I/O

SDA in I

2C for CPU interface

PWM_CTL

15

O

PWM control signal (Detail description in PWM

Operation Section)

CLK_1M

16

I

Free Running Clock (default: 1MHz)

VDD

17

Power Supply

CLK_1M_O

18

O

Feedback of free Running Clock

RESET_B

19

I

System Reset ( active LOW)

R_OSD

20

I

OSD Color Red

G_OSD

21

I

OSD Color Green

B_OSD

22

I

OSD Color Blue

EN_OSD

23

I

OSD Mixer Enable

=0, No OSD output

=1,R_OUT[7:0]= {R_OSD repeat 8 times}

G_OUT[7:0]= {G_OSD repeat 8 times }

B_OUT[7:0]= {B_OSD repeat 8 times }

SCAN_EN

24

I

Manufacturing test pin (NC)

TEST_EN

25

I

Manufacturing test pin (NC)

VCLK01

26

I

Input Clock 1

FCLK0

27

O

Input PLL Feedback Clock

VCLK00

28

I

Input Clock 0

FCLK1

29

O

Output PLL Feedback Clock

VCLK1

30

I

Output PLL Output Clock

HSYNC_O

31

O

Output HSYNC (the polarity is programmable through

CPU, default is active low)

VSYNC_O

32

O

Output VSYNC (the polarity is programmable through

CPU, default is active low)

DCLK_OUT

33

O

Output Clock to Control Panel (the polarity is

programmable through CPU)

DE_OUT

34

O

Output Display Enable for Panel (the polarity is

programmable through CPU, default is active HIGH)

GND

35

Ground

VDD

36

Power Supply

R_OUT0_E

37

O

Output Color Red Even Pixel (left pixel)

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