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CS7622-IQ Datasheet(PDF) 11 Page - Cirrus Logic |
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CS7622-IQ Datasheet(HTML) 11 Page - Cirrus Logic |
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11 / 36 page  CS7622 DS322PP1 11 During fixed gain mode the time constant is a little different. In order to achieve no ringing in the settling use, for offset range = 1, and for offset range = 0. The 9 MSBs of the black level accumulator can be read or written through a register. If written, the LSBs are set to zero. The black level is set to “8” in a 10-bit digital output representation. In a 13-bit representation, it is set to “64.” The power-up de- fault value in the accumulator is at mid level. Also note that the black level adjust loop can be disabled. In addition, the black level can be pro- grammed through the serial port. 3.3 Gain Adjust Block In order to increase the dynamic range of the ADC, a variable gain, whose value is determined by the signal level, is applied to each pixel. This allows for 13 bits of dynamic range and 10 bits of resolu- tion after accounting for the significance of the ADC output bits. The gain applied in the analog is illustrated in the transfer curve in Figure 7. Once the signal is digitized, the gain adjust block uses the gain information for a given pixel word and shifts its bits accordingly. For example, using a full scale level of 1.0 V, if Vin = 0.3 V, the VGA would choose a gain of 2X so the ADC input is 0.6 V. The 10-bit output of the ADC (with no black level) is (0.6/1.0) × 1024 = 614, or “1001100110.” in bina- ry. The gain adjust block will take this value plus the bits representing the 2x gain and divide the out- put by two (shift right by 1). The output of the gain adjust block is then “0100110011.000.” Note that the decimal point is virtual, having no existence in silicon. It is representing the fact that we keep 3 ex- tra bits of lower significance in the output. In the same manner, if Vin = 0.75 V, a gain of 1X would be chosen and the output of the gain adjust block For a fixed gain of 1: For a fixed gain of 2: For a fixed gain of 4: For a fixed gain of 8: ADC Z-1 + + 10 7 9 DAC BINARY TO THERM Z-1 FU FP FU = UPDATE FREQUENCY FP = PIXEL FREQUENCY K CLIP CDS/VGA Σ VIN FROM SERIAL INTERFACE + BLK LVL LOOP ‘64’ Figure 10. Black level adjustment loop - GAIN REG τ 1 1 nK 8 ------- – ln ---------------------------- – 1 fu ----- = τ 1 1 nK 4 ------- – ln ---------------------------- – 1 fu ----- = τ 1 1 nK 2 ------- – ln ---------------------------- – 1 fu ----- = τ 1 1nK – () ln --------------------------- – 1 fu ----- = n K ---- 1 ≤ n 2K ------- 1 ≤ |
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