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ST22N256 Datasheet(PDF) 3 Page - STMicroelectronics |
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ST22N256 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 8 page 3/8 ST22N256 DESCRIPTION The ST22N256 is a member of the SmartJ™ plat- form using a 32-bit Reduced Instruction Set Com- puter (RISC) core to execute both Native RISC instructions and JavaCard™ 2.x Technology in- struction (byte codes) directly. Direct JavaCard™ byte code execution provides high performance advantage over processors that emulate the JavaCard™ byte code instruction set. The product features a 24-bit wide linear address- ing capability and includes User ROM, User RAM, and User EEPROM. Memory and Peripheral accesses are controlled by a Memory Protection Unit that allows to imple- ment firewalls between applications. Memories are accessed via two different buses, allowing simultaneous accesses to code and data. Memory load and stores can be performed at byte, short (2-bytes), or word (4-bytes) granularity, with optional pointer auto increment. The ST22 core includes dedicated DES instruc- tions for Secret Key cryptography, and a fast Mul- tiply and Accumulate instruction for Public Key cryptography (RSA) and Elliptic Curve cryptogra- phy, and a CRC instruction. The ST22 core also includes specific instructions for security. The product has clock and power management, 2 User configurable Timers, a Central Interrupt Con- troller and a Random Number Generator. Figure 2. SmartJ™ Platform EEPROM Architecture POWER MANAGEMENT 32-bit RISC CORE CLOCK MANAGEMENT MPU RAM BUS 2 BUS 1 PERIPHERALS ISO 7816 ROM EEPROM |
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