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AD8315ARM-REEL Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD8315ARM-REEL
Descripción Electrónicos  50 dB GSM PA Controller
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AD8315ARM-REEL Datasheet(HTML) 10 Page - Analog Devices

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REV. B
AD8315
–10–
Control Loop Dynamics
In order to understand how the AD8315 behaves in a complete
control loop, an expression for the current in the integration
capacitor as a function of the input VIN and the setpoint voltage
VSET must be developed. Refer to Figure 3.
SETPOINT
INTERFACE
LOGARITHMIC
RF DETECTION
SUBSYSTEM
3
1
VSET
RFIN
4
CFLT
FLTR
7
VAPC
ISET = VSET/4.15k
IDET
IERR
IDET = ISLPLOG10 (VIN/VZ)
VSET
VIN
1.35
Figure 3. Behavioral Model of the AD8315
First, the summed detector currents are written as a function of
the input:
II
V
V
DET
SLP
IN
Z
=
log
(
/
)
10
(3)
where IDET is the partially filtered demodulated signal, whose
exact average value will be extracted through the subsequent
integration step; ISLP is the current-mode slope and has a value
of 115
mA per decade (that is, 5.75 mA/dB); VIN is the input in
volts-rms; and VZ is the effective intercept voltage, which, as
previously noted, is dependent on waveform but is 316
mV rms
(–70 dBV) for a sine wave input. Now the current generated by
the setpoint interface is simply:
IV
k
SET
SET
=W
/.
415
(4)
The difference between this current and IDET is applied to the
loop filter capacitor CFLT. It follows that the voltage appearing on
this capacitor, VFLT, is the time integral of the difference current:
Vs
I
I
sC
FLT
SET
DET
FLT
()
(
)/
=
(5)
=
W
Vk
I
V
V
sC
SET
SLP
IN
Z
FLT
/.
log
(
/
)
415
10
(6)
The control output VAPC is slightly greater than this, since the
gain of the output buffer is
¥1.35. Also, an offset voltage is
deliberately introduced in this stage; this is inconsequential
since the integration function implicitly allows for an arbitrary
constant to be added to the form of Equation 6. The polarity is
such that VAPC will rise to its maximum value for any value of
VSET greater than the equivalent value of VIN. In practice, the
VAPC output will rail to the positive supply under this condition
unless the control loop through the power amplifier is present.
In other words, the AD8315 seeks to drive the RF power to its
maximum value whenever it falls below the setpoint. The use
of exact integration results in a final error that is theoretically
zero, and the logarithmic detection law would ideally result in a
constant response time following a step change of either the
setpoint or the power level, if the power-amplifier control
function were likewise linear-in-dB. This latter condition is
rarely true, however, and it follows that in practice, the loop
response time will depend on the power level, and this effect can
strongly influence the design of the control loop.
Equation 6 can be restated as:
Vs
VV
V
V
sT
APC
SET
SLP
IN
Z
()
log
(
/
)
=
-
10
(7)
where VSLP is the volts-per-decade slope from Equation 1, having
a value of 480 mV/decade, and T is an effective time constant for
the integration, being equal to 4.15 k
W ¥ CFLT/1.35; the resistor
value comes from the setpoint interface scaling Equation 4 and
the factor 1.35 arises because of the voltage gain of the buffer.
So the integration time constant can be written as:
TC
in s when C is
in nF
FLT
= 307
.,
m
expressed
(8)
To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function actu-
ally is linear-in-dB. Also use voltages to express the signals at
the power amplifier input and output, for the moment. Let the
RF output voltage be VPA and its input be VCW. Further, to
characterize the gain control function, this form is used:
VG V
PA
O
CW
VV
APC
GBC
=
10
(/)
(9)
where GO is the gain of the power amplifier when VAPC = 0 and
VGBC is the gain-scaling. While few amplifiers will conform so
conveniently to this law, it provides a clearer starting point for
understanding the more complex situation that arises when the
gain control law is less ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is:
Vs
VV
V
V
kG V
V
sT
APC
SET
GBC
SLP
GBC
O
CW
Z
O
()
()/
log
/
=
()
+
10
1
(10)
where k is the coupling factor from the output of the power
amplifier to the input of the AD8315 (e.g.,
¥ 0.1 for a “20 dB
coupler”), and TO is a modified time constant (VGBC /VSLP)T.
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level VSET or the carrier input VCW. Second, it reveals that the
final value of the control voltage VAPC will be determined by
several fixed factors:
Vt
V
V
V
kG V
V
APC
SET
GBC
SLP
O
CW
Z
=•
() = ()
(
)
/– log
/
10
(11)
Example
Assume that the gain magnitude of the power amplifier runs
from a minimum value of
¥0.316 (–10 dB) at VAPC = 0 to ¥100
(40 dB) at VAPC = 2.5 V. Applying Equation 9, GO = 0.316 and
VGBC = 1 V. Using a coupling factor of k = 0.0316 (that is, a
30 dB directional coupler) and recalling that the nominal value of
VSLP is 480 mV and VZ = 316 V for the AD8315, first calculate
the range of values needed for VSET to control an output range
of 33 dBm to –17 dBm. This can be found by noting that, in
the steady state, the numerator of Equation 7 must be zero,
that is:
VV
kV
V
SET
SLP
PA
Z
=
log
(
/
)
10
(12)
when VIN is expanded to kVPA, the fractional voltage sample of
the power amplifier output. Now, for +33 dBm, VPA = 10 V rms,
this evaluates to:
VmV
V
V
SET ()
.
log
(
/
)
.
max
==
048
316
316
1 44
10
m
(13)
For a delivered power of –17 dBm, VPA = 31.6 mV rms:
VmV
V
V
SET ()
.
log
(
/
)
.
min
==
048
1
316
024
10
m
(14)


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