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CS42528 Datasheet(PDF) 3 Page - Cirrus Logic |
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CS42528 Datasheet(HTML) 3 Page - Cirrus Logic |
3 / 91 page DS586PP5 3 CS42528 5. REGISTER QUICK REFERENCE .......................................................................................... 42 6. REGISTER DESCRIPTION .................................................................................................... 47 6.1 Memory Address Pointer (MAP) ....................................................................................... 47 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 47 6.3 Power Control (address 02h)............................................................................................ 48 6.4 Functional Mode (address 03h) ........................................................................................ 49 6.5 Interface Formats (address 04h) ...................................................................................... 50 6.6 Misc Control (address 05h) .............................................................................................. 52 6.7 Clock Control (address 06h) ............................................................................................. 53 6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 55 6.9 RVCR Status (address 08h) (Read Only)......................................................................... 55 6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only).......................... 56 6.11 Volume Transition Control (address 0Dh) ...................................................................... 57 6.12 Channel Mute (address 0Eh).......................................................................................... 59 6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ........................ 59 6.14 Channel Invert (address 17h) ......................................................................................... 59 6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................ 60 6.16 ADC Left Channel Gain (address 1Ch) .......................................................................... 62 6.17 ADC Right Channel Gain (address 1Dh) ........................................................................ 62 6.18 Receiver Mode Control (address 1Eh) ........................................................................... 62 6.19 Receiver Mode Control 2 (address 1Fh) ........................................................................ 63 6.20 Interrupt Status (address 20h) (Read Only) ................................................................... 64 6.21 Interrupt Mask (address 21h) ......................................................................................... 65 6.22 Interrupt Mode MSB (address 22h) Interrupt Mode LSB (address 23h)................................................................................ 65 6.23 Channel Status Data Buffer Control (address 24h) ........................................................ 66 6.24 Receiver Channel Status (address 25h) (Read Only) .................................................... 67 6.25 Receiver Errors (address 26h) (Read Only) ................................................................... 68 6.26 Receiver Errors Mask (address 27h) .............................................................................. 69 6.27 MuteC Pin Control (address 28h) ................................................................................... 69 6.28 RXP/General Purpose Pin Control (addresses 29h to 2Fh) ........................................... 70 6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only)......................... 72 6.30 C-bit or U-bit Data Buffer (addresses 3Ah to 51h) (Read Only) ..................................... 72 7. PARAMETER DEFINITIONS .................................................................................................. 73 8. REFERENCES ........................................................................................................................ 74 9. PACKAGE DIMENSIONS ................................................................................................... 75 THERMAL CHARACTERISTICS ........................................................................................... 75 10. APPENDIX A: EXTERNAL FILTERS ................................................................................... 76 10.1 ADC Input Filter ............................................................................................................. 76 10.2 DAC Output Filter .......................................................................................................... 76 11. APPENDIX B: S/PDIF RECEIVER ....................................................................................... 77 11.1 Error Reporting and Hold Function ................................................................................ 77 11.2 Channel Status Data Handling ...................................................................................... 77 11.2.1 Channel Status Data E Buffer Access .............................................................. 78 11.2.1a One Byte mode .................................................................................. 78 11.2.1b Two Byte mode .................................................................................. 78 11.2.2 Serial Copy Management System (SCMS) ....................................................... 79 11.3 User (U) Data E Buffer Access ...................................................................................... 79 11.3.1 Non-Audio Auto-Detection ................................................................................ 79 11.3.1a Format Detection ............................................................................... 79 |
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