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CD4071B Datasheet(PDF) 1 Page - Silicon Supplies |
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CD4071B Datasheet(HTML) 1 Page - Silicon Supplies |
1 / 5 page CMOS High Voltage Logic – CD4071B CMOS Quad 2-Input OR Gate in bare die form High Input Voltage up to 20V Symmetrical Output Characteristics Max input current 1µA at 18V over full Military Temperature Range Low Power TTL compatible Die Size (Unsawn) 1270 x 940 50 x 37 µm mils Minimum Bond Pad Size 106 x 106 4.17 x 4.17 µm mils Die Thickness 635 (±20) 25 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Specified at 5V, 10V & 15V Direct drop-in replacement for obsolete components in long term programs. Rev 1.0 19/09/18 Features: The following part suffixes apply: The CD4071B provides the system designer with direct implementation of the positive-logic OR function. The device has equal source and sink current capabilities and conforms to standard B series output drive. Device outputs are buffered which improves transfer characteristics by providing very high gain. The device is capable of driving x2 low power TTL loads or x1 LSTTL load. The CD4071B is primarily used for higher voltage acceptance and where low power dissipation and/or high noise immunity are required. Ordering Information Description Die Dimensions in µm (mils) 1270 (50) No suffix - MIL-STD-883 /2010B Visual Inspection “H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\quality\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 635µm(25 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com |
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