NOTES (Unless Otherwise Specified):

1.

All dimensions are in millimeters.

2.

Six (6) solder bumps are Eutectic solder 63/37Pb with diameter f0.38 − 0.40 mm.

3.

Backside surface is coated with a Ti/Nl/Ag layer.

4.

Non-solder mask defined copper landing pad.

5.

The flat side of wafers is oriented at the bottom.

6.

D is location of Pin 1P.

e

e

e

e

e

E

s

e

S1

D

R

Q

P

12

Backside Labels

Recommended Land

Note 3

6 Bumps (Note 2)

Bump Diameter:

f0.38 − 0.40 mm

A1

A2

A

Si8407DB

Vishay Siliconix

www.vishay.com

6

Document Number: 72254

S-50066—Rev. B, 17-Jan-05

PACKAGE OUTLINE

MICRO FOOT: 6-BUMP (2.4 X 2.0, 8-mm PITCH)

PAD DISTRIBUTION TABLE

P

Q

R

1

Drain

Gate

Source

2

Drain

Source

Source

MILLIMETERS*

INCHES

Dim

Min

Max

Min

Max

A

0.600

0.650

0.0236

0.0256

0.260

0.290

0.0102

0.0114

0.340

0.360

0.0134

0.0142

b

0.370

0.410

0.0146

0.0161

D

1.920

2.000

0.0756

0.0787

E

2.320

2.400

0.0913

0.0945

e

0.750

0.850

0.0295

0.0335

S

0.370

0.400

0.0150

0.0157

S1

0.580

0.600

0.0228

0.0236

* Use millimeters as the primary measurement.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and

Package Reliability represent a composite of all qualified locations.

For related documents such as package/tape drawings, part marking, and reliability data, see

http://www.vishay.com/ppg?72254

.