W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers

6

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AC ELECTRICAL CHARACTERISTICS (continued)

(Devices tested on their respective evaluation kits (EV kits); LNA input port is driven with a 50

Ω source; LNA output port is terminated

with 50

Ω load, mixer differential input port is driven through a 1:4 impedance balun with a 50Ω source; baseband I/Q output differential

load = 10k

Ω || 5pF; reference oscillator input: 19.2MHz (MAX2390/MAX2391/MAX2392/MAX2393), 26MHz (MAX2401), 15.36MHz

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ON-CHIP VCO

MAX2391/MAX2396

4220

4340

MAX2392

4020

4050

MAX2393

3800

3840

MAX2390/MAX2400

3860

3980

VCO Frequency

(VCO Range is 2x the LO Range)

MAX2401

3610

3760

MHz

Phase Noise

ΦNAt 10MHz offset; locked (Note 3)

-139

-133

dBc/Hz

Pulling

From IDLE mode to ON mode (Note 3)

0.5

1

Pushing

13

MHz/V

VCO INTERFACE TO EXTERNAL SYNTHESIZER (MAX2396/MAX2400)

MAX2396

130

300

VCO Tuning Gain

Referred to the VCO

frequency (2x RFLO)

MAX2400

100

270

MHz/V

MAX2396

1406.67 1426.67 1446.67

VCO Output Frequency

Output to synthesizer is

MAX2400

1286.67 1306.67 1326.67

MHz

VCO Output Differential Voltage

(Note 12)

180

VCO Tuning Voltage Range

0.4

2.3

V

INTEGER-N RF SYNTHESIZER (MAX2390–MAX2393, MAX2401)

Main PLL Integer Division Ratio

15-bit register (64/65 dual-modulus prescaler),

4032

10700

32767

Reference Frequency Range

10

19.2

40

MHz

REFDIV Reference-Divider Ratio

9-bit register

16

96

511

Charge-Pump Output Current

(Sink or Source)

CONFIG:CP1 = 1, CONFIG:CP0 = 1,

2.0

2.5

3.0

mA

Charge-Pump Leakage Current

10

nA

SYSTEM TIMING

Turn-On Time Including

DC Offset Cancellation

From IDLE mode to ON mode VGA set to

maximum gain with -40dBm signal at

demodulator input (Note 3)

30

60

µs

3-WIRE SERIAL INTERFACE TIMING

Data to Clock Setup

Per timing diagram

20

ns

Data to Clock Hold Time

Per timing diagram

10

ns

Clock Pulse-Width High

Per timing diagram

20

ns

Clock Pulse-Width Low

Per timing diagram

20

ns

Clock to Load Enable/Setup Time

Per timing diagram

20

ns

Clock Frequency

20

MHz

Note 2: All min and max specifications are measured over this frequency range.

Note 3: Guaranteed by design and characterization.