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GD5F2GQ4RFZJG Datasheet(PDF) 22 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F2GQ4RFZJG Datasheet(HTML) 22 Page - GigaDevice Semiconductor (Beijing) Inc. |
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22 / 46 page  SPI(x1/x2/x4) NAND Flash 2G 22 11 PROGRAM OPERATIONS 11.1 Page Program The PAGE PROGRAM operation sequence programs 1 byte to 2176 bytes of data with in a page. The page program sequence is as follows: • 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4) • 06H (WRITE ENABLE) • 10H (PROGRAM EXECUTE) • 0FH (GET FEATURE command to read the status) Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache register that is 2176 bytes long. If more than 2176bytes are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH. Figure11-1 shows the PROGRAMLOAD operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITEENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored. Note: 1. The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h) command and RESET (FFh) command. 2. When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller outputs 0xFF data to the NAND for the address that data was not loaded by Program Load (02h) command. 3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, SPI- NAND controller outputs contents of Cache Register to the NAND. 4. The addressing should be done in sequential order in a block. |
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