Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼
Nombre de pieza
         Descripción


GD5F1GQ4UFYIH Datasheet(Hoja de datos) 23 Page - GigaDevice Semiconductor (Beijing) Inc.

No. de Pieza. GD5F1GQ4UFYIH
Descripción  SPI(x1/x2/x4) NAND Flash
Descarga  49 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de inicio  http://www.gigadevice.com/
Logo 

 23 page
background image
SPI(x1/x2/x4) NAND Flash
1G
23
11 PROGRAM OPERATIONS
11.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to 2112 bytes of data with in a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache
register that is 2112 bytes long. If more than 2112 bytes are loaded, then those additional bytes are ignored by the cache
register. The command sequence ends when CS# goes from LOW to HIGH. Figure11-1 shows the PROGRAMLOAD
operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must
be issued. As with any command that changes the memory contents, the WRITEENABLE must be executed in order to set
the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.
Note:
1.
The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h) command and
RESET (FFh) command.
2.
When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller outputs 0xFF
data to the NAND for the address that data was not loaded by Program Load (02h) command.
3.
When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, SPI-NAND controller
outputs contents of Cache Register to the NAND.
4.
The addressing should be done in sequential order in a block.




Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49 


Datasheet Download




Enlace URL

¿ALLDATASHEET es útil para Ud.?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl