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GD5F2GQ4UEZIS Datasheet(Hoja de datos) 19 Page - GigaDevice Semiconductor (Beijing) Inc.

No. de Pieza. GD5F2GQ4UEZIS
Descripción  SPI(x1/x2/x4) NAND Flash
Descarga  57 Pages
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Fabricante  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de inicio  http://www.gigadevice.com/
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SPI(x1/x2/x4) NAND Flash
2G
19
8.6 Read From Cache Dual IO (BBH)
The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the
capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and a dummy byte
by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit
per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically
to the next higher address after each byte of data shifted out until the boundary wrap bit.
Figure8-5. Read From Cache Dual IO Sequence Diagram
Command
0
1
2
3
4
5
6
7
BBH
CS#
SCLK
SI(SIO0)
SO(SIO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
A7-0
Dummy
Byte1
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(SIO0)
SO(SIO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte2
Byte3
Byte4
Byte5
dummy<3:0>, A11-8




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