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GD5F2GQ4UEZIS Datasheet(Hoja de datos) 14 Page - GigaDevice Semiconductor (Beijing) Inc.

No. de Pieza. GD5F2GQ4UEZIS
Descripción  SPI(x1/x2/x4) NAND Flash
Descarga  57 Pages
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Fabricante  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de inicio  http://www.gigadevice.com/
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 14 page
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SPI(x1/x2/x4) NAND Flash
2G
14
7
FEATURE OPERATIONS
7.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP and block locking can be enabled or disabled by setting specific feature bits (shown in the
following table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H)
command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table7-1. Features Settings
Register
Addr.
7
6
5
4
3
2
1
0
Protection
A0H
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
Feature
B0H
OTP_PRT
OTP_EN
Reserved
ECC_EN
Reserved
Reserved
Reserved
QE
Status
C0H
Reserved
Reserved
ECCS1
ECCS0
P_FAIL
E_FAIL
WEL
OIP
Feature
D0H
HOLDB/RST
DS_S1
DS_S0
Reserved
Reserved
Reserved
Reserved
Reserved
Status
F0H
Reserved
Reserved
ECCSE1
ECCSE0
Reserved
Reserved
Reserved
Reserved
Note:
If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
00h is the default data byte value for Output Driver Register after power-up.
HOLDB/RST is for WSON8 Package only. By default HOLDB/RST registers is 0 after power-on-reset or hardware
reset, and this bit default is HOLD function.
Figure7-1. Get Features Sequence Diagram
Command
0
1
2
3
4
5
6
7
0FH
CS#
SCLK
SI
SO
High-Z
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
1 byte address
Data byte
MSB
Note: The output would be updated by real-time, until CS# is driven high.




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