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GD25B257D Datasheet(PDF) 46 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D Datasheet(HTML) 46 Page - GigaDevice Semiconductor (Beijing) Inc. |
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46 / 92 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 46 8.17. Page Program (PP 02H or 4PP 12H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low sending Page Program command 3 or 4-Byte address on SI at least 1 Byte data on SI CS# goes high. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) is not executed. When ECC is enabled (ECC=1 in Extended Register), Page Program instruction must program minimum aligned 8- Byte (A[2:0]=0,0,0) data or multiple of aligned 8-Byte data granularities, up to the 256-Byte page. Every aligned 8-Byte memory can only be programmed once before any Erase operation at that address. Figure 42. Page Program Sequence Diagram (ADS=0) Command 0 1 2 3 4 5 6 7 02H CS# SCLK SI 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 32 33 34 35 7 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 36 37 38 39 |
Número de pieza similar - GD25B257D |
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Descripción similar - GD25B257D |
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