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TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No.
Pin label
Type
Description
64
Txen0
O
GMII/MII transmit enable
65
Gtxclk0
O
GMII transmit clock
66
Vss 3.3
G
Digital ground for I/O
67
Txer0
I/Opd Transmit Error
68
Txclk0
I
MII transmit clock
69
Crs0
Is
MII carrier sense indication
70
Col0
Is
MII collision indication
71
Rxer0
Is
Receive Error
72
Vdd 2.0
P
Digital +2.0V power supply for core
73
Rxclk0
I
MII receive clock
74
Rxdv0
Is
GMII/MII data valid
75
Rxd00
Is
GMII receive data – least significant nibble.
MII receive data
76
Rxd01
Is
GMII receive data – least significant nibble.
MII receive data
77
Rxd02
Is
GMII receive data – least significant nibble.
MII receive data
78
Vss 2.0
G
Digital ground for core
79
Rxd03
Is
GMII receive data – least significant nibble.
MII receive data
80
Rxd04
Is
GMII receive data – most significant nibble
81
Rxd05
Is
GMII receive data – most significant nibble
82
Rxd06
Is
GMII receive data – most significant nibble
83
Rxd07
Is
GMII receive data – most significant nibble
84
Vdd 3.3
P
Digital +3.3V power supply for I/O
85
Vss 3.3
G
Digital ground for I/O
86
Vdd 2.0
P
Digital +2.0V power supply for core
87
Vss 2.0
G
Digital ground for core
88
Vdd 3.3
P
Digital +3.3V power supply for I/O
89
Gnd
I
90
Vss 3.3
G
Digital ground for I/O
91
Gnd
I
92
Vdd 3.3
P
Digital +3.3V power supply for I/O
93
SelSck
Is
Selects the source for the system clock.
Selsck – ‘1’ – sysck is driven by a 25Mhz external clock.
94
NC
NA
Reserved for future use
95
NC
NA
Reserved for future use
96
NC
NA
Reserved for future use
97
NC
NA
Reserved for future use
98
NC
NA
Reserved for future use
99
NC
NA
Reserved for future use
100
NC
NA
Reserved for future use
Confidential.
8/49
July 29, 2003
Copyright © 2003, IC Plus Corp.
TC9204M-DS-R05
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