SN74CBTD3305C

DUAL FET BUS SWITCH WITH LEVEL SHIFTING

5V BUS SWITCH WITH 2V UNDERSHOOT PROTECTION

SCDS126A − SEPTEMBER 2003 − REVISED OCTOBER 2003

6

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

FOR LEVEL SHIFTER

VOH

VOL

CL

(see Note A)

TEST CIRCUIT

S1

7 V

Open

GND

RL

RL

tPLH

tPHL

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VOH

VOL

0 V

VOL + V∆

VOH − V∆

0 V

Output

Control

(VIN)

3 V

3.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (tpd(s))

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state

resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

50

Ω

VG1

VCC

DUT

50

Ω

VIN

50

Ω

VG2

50

Ω

VI

TEST

RL

S1

V∆

CL

5 V

± 0.5 V

VCC

VI

tPLZ/tPZL

tpd(s)

5 V

± 0.5 V

5 V

± 0.5 V

Open

7 V

Open

500

Ω

500

Ω

500

Ω

VCC or GND

GND

VCC

50 pF

50 pF

50 pF

0.3 V

0.3 V

Output

Control

(VIN)

Input Generator

Input Generator

VO

tPHZ/tPZH

Figure 3. Test Circuit and Voltage Waveforms