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TWR-LS1021A Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

No. de pieza TWR-LS1021A
Descripción Electrónicos  TWR-LS1021A Reference Manual
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
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TWR-LS1021A Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

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Architecture
TWR-LS1021A Reference Manual, Rev. 0
Freescale Semiconductor
2-17
2.12.1
IFC chip select
IFC chip select signals are assigned in Table 2-11:
NOTE
IFC CS2 and CS3 are multiplexed with I2C3 SCL and SDA, the selection is
done in CPLD.
2.12.2
Memory map
Memory addresses are defined by software and rearranged externally by the “cfg_lbmap” functions, there
are many possible memory maps. The default memory map shown in Table 2-12 reflects selecting the first
line in Table 2-11 (with NOR flash as the boot device).
2.12.3
Virtual banks
As noted earlier, the “virtual bank” feature is available when the NOR flash is selected as the device
connected to IFC_CS0_B. In that case, the value will be divided into two banks of XOR gates, which
toggle the MSB’s of the NOR address, as shown in Figure 2-12.
Figure 2-12. NORFlash virtual bank address XOR
Table 2-11. IFC chip select mapping
Device
NOR
Flash
CPLD
ELEV
-C78 pin
ELEV
-C77 pin
ELEV
-C76 pin
CS mapping
CS0
CS1
CS1
CS2
CS3
Table 2-12. IFC 32b address mapping
32b Address Range
Size
Device
IFC_CS
Description
0x8000_0000 - 0xBFFF_FFFF
1GB
DDR DRAM
-
0x0100_0000 - 0x0FFF_FFFF
240MB
CCSR Space
-
0x7FB0_0000 - 0x7FB0_FFFF
64KB
CPLD Registers
1
0x6000_0000 - 0x67FF_FFFF
128MB
3.3V NOR Flash
0
Note: This address is only valid if boot software opts to implement it - check software documentation for actual
memory map.


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