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TWR-LS1021A Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc |
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TWR-LS1021A Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 71 page  LS1021A/LS1020A Overview TWR-LS1021A Reference Manual, Rev. 0 Freescale Semiconductor 1-3 1.3 Board features The features of the TWR-LS1021A reference board are as follows: • SERDES Connections — Four lanes supporting: – PCI Express: supporting Gen 1 and Gen 2 –SGMII – SATA 2.0/3.0 – Integrated USB3 PHY features dedicated SERDES lane • DDR Controller — Supports rates of up to 1600 MHz data-rate — Supports 1 GB unbuffered DDR3L SDRAM discrete devices (32-bit bus) — DDR power supplies 1.35 V to all devices with automatic tracking of VTT • IFC/Local Bus — NOR: 16-bit, non-multiplexed, up to 128 MB – NOR devices support two virtual banks — CPLD: 8-bit registers in CPLD to configure some mux/demux selection • Ethernet — One on-board RGMII 10/100/1G ethernet port — IEEE1588 test header on board — Two on-board SGMII 10/100/1G ethernet ports • System Logic CPLD — Manages system power and reset sequencing — LCD 2-bit FDI convert to 1-bit — Latch IFC address/data multiplexed signals. — Signal mux/demux function (for example, CAN3/4_TX/RX, LCD and UCC) — Level shifter (for example, USB2 signals) — NOR bank selection logic •Clocks — System and DDR clock (SYSCLK, “DDRCLK”) – Switch selectable to one of four settings: 66 MHz, 80 MHz, 83 MHz and 100 MHz for system clock — 100 MHz new single-source DIFF_SYCLK_/DIFF_SYSCLK_N input to processor which supports to core/platform SYSCLK, DDR controller (DDRCLK), and USB controller (USBCLK) — SERDES clocks – Provides clocks to all SerDes blocks and slots – 100 MHz or 125 MHz |
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