4 / 10 page
Low Power CMOS SRAM
32K X8 Bits
UC62LV0256
-35/-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
FIGURE 1A
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
FIGURE 1B
667
Ω
TERMINAL EQUIVALENT
OUTPUT
1.73V
GND
V
CC
5ns
5ns
10%
90%
90%
10%
ALL INPUT PULSES
FIGURE 2
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=3.0V)
READ CYCLE
UC62LV0256-35
UC62LV0256-70
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max
Min
Typ
Max
UNIT
tAVAX
tRC
Read Cycle Time
35
-
-
70
-
-
ns
tAVQV
tAA
Address Access Time
-
-
35
-
-
70
ns
tELQV
tCE
Chip Select Access Time
-
-
35
-
-
70
ns
tGLQV
tOE
Output Enable to Output Valid
-
-
15
-
-
50
ns
tELQX
tCLZ
Chip Select to Output Low Z
5
-
-
10
-
-
ns
tGLQX
tOLZ
Output Enable to Output Low Z
5
-
-
10
-
-
ns
tEHQZ
tCHZ
Chip Deselect to Output in High Z
0
-
35
0
-
35
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
0
-
20
0
-
30
ns
tAXOX
tOH
Address Chang to Output Change
10
-
-
10
-
-
ns
U-Chip Technology Corp. LTD.
Revision 2.0
Reserves the right to modify document contents without notice.
PAGE
4
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
