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CDCDB2000 Datasheet(Hoja de datos) 16 Page - Texas Instruments

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No. de Pieza. CDCDB2000
Descripción  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
Descarga  33 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 16 page
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SBI
Controller
CDCDB2000
(1)
CDCDB2000
(2)
DATA
CLK
SHFT_LD# (2)
SHFT_LD# (1)
D
Q
Q
>
D
Q
Q
>
Q0
Q1
To Q2
OE1
OE0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
D
Q
Q
>
OE19
From Q18
Shift
Register
Output
Register
(Default is 1)
DATA
CLK
SHFT_LD#
Mask0
Mask1
Mask19
To Output Logic
From SMBus Mask
Registers
Side-Band Interface
16
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Programming (continued)
Figure 7. SMBus Mask Register and SBI Shift Register Logic
7.5.1 SMBus
SMBus programming is described in SMBus, and the registers are described in Register Maps .
7.5.2 SBI
Side-Band Interface (SBI) is a simple 3-wire serial interface. This interface consists of DATA, CLK and
SHFT_LD# pins. When the SHFT_LD# pin is high, the rising edge of CLK clocks DATA into a shift register. After
shifting data, the falling edge of SHFT_LD# loads the shift register contents into the Output Register. Both the
SBI and the traditional SMBus interface feed common output enable/disable synchronization logic, which ensures
glitch-free enable and disable outputs regardless of the method used.
SBI can be configured at a system level in three ways: star topology, daisy chain topology, and directly. The star
topology is shown in Figure 8. The daisy chain topology is shown in Figure 9.
Figure 8. SBI Star Topology




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