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CDCDB2000 Datasheet(Hoja de datos) 24 Page - Texas Instruments

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No. de Pieza. CDCDB2000
Descripción  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
Descarga  33 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 24 page
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PCIe Gen 4-5
Clock
Generator
CDCDB2000
20x LP-HSCL Output Buffer
SMBus
Control
OE#
Control
LP-HCSL
PCIe PHY
PCIe PHY
PCIe PHY
PCIe PHY
LP-HCSL
20
PCIe PHY
PCIe PHY
PCIe Device
Side-Band
Interface
Control Interface
24
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
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Copyright © 2019, Texas Instruments Incorporated
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The CDCDB2000 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.
It is used to create, and distribute, up to 20 copies of a typically 100-MHz clock.
8.2 Typical Application
Figure 10 shows a CDCDB2000 typical application. In this application, a clock generator provides a 100-MHz
reference to the CDCDB2000 which then distributes that clock to PCIe endpoints. The clock generator may be a
discrete clock generator like the LMK03328 or it may be integrated in a larger component such as a PCH or
application processor.
Figure 10. Typical Application
8.2.1 Design Requirements
Consider a typical server motherboard application which needs to distribute a 100-MHz PCIe reference clock
from the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:
Clock Input:
100-MHz LP-HCSL
Clock Output:
2x 100-MHz to processors, LP-HCSL
2x 100-MHz to riser/retimer, LP-HCSL
2x 100-MHz to DDR memory controller, LP-HCSL
The section below describes the design procedure to configure the CDCDB2000 to output the frequencies for the
above scenario.
8.2.2 Detailed Design Procedure
The following items must be determined before starting design of a CDCDB2000 socket:
Output Enable Control Method
SMBus address




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