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CDCDB2000 Datasheet(Hoja de datos) 4 Page - Texas Instruments

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No. de Pieza. CDCDB2000
Descripción  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
Descarga  33 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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4
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
CK5_P
M9
O
LP-HCSL differential clock output of channel 5. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin L8
(OE5# / DATA) is recommended to be either in DATA mode or pulled high.
CK5_N
M10
O
CK6_P
M11
O
LP-HCSL differential clock output of channel 6. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin L10
(OE6# / CLK) is recommended to be either in CLK mode or pulled high.
CK6_N
M12
O
CK7_P
L12
O
LP-HCSL differential clock output of channel 7. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
K11 (OE7#) is recommended to be pulled high to disable channel 7 output.
CK7_N
K12
O
CK8_P
J12
O
LP-HCSL differential clock output of channel 8. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
H11 (OE8#) is recommended to be pulled high to disable channel 8 output.
CK8_N
H12
O
CK9_P
G12
O
LP-HCSL differential clock output of channel 9. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
E12 (OE9#) is recommended to be pulled high to disable channel 9 output.
CK9_N
F12
O
CK10_P
D12
O
LP-HCSL differential clock output of channel 10. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
E11 (OE10# / SHFT_LD#) is recommended to be either in SHFT_LD# mode or
pulled high.
CK10_N
C12
O
CK11_P
B12
O
LP-HCSL differential clock output of channel 11. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
C11 (OE11#) is recommended to be pulled high to disable channel 11 output.
CK11_N
A12
O
CK12_P
A11
O
LP-HCSL differential clock output of channel 12. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect, and pin
B10 (OE12#) is recommended to be pulled high to disable channel 12 output.
CK12_N
A10
O
CK13_P
A9
O
LP-HCSL differential clock output of channel 13. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK13_N
A8
O
CK14_P
A7
O
LP-HCSL differential clock output of channel 14. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK14_N
A6
O
CK15_P
A5
O
LP-HCSL differential clock output of channel 15. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK15_N
A4
O
CK16_P
A3
O
LP-HCSL differential clock output of channel 16. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK16_N
A2
O
CK17_P
A1
O
LP-HCSL differential clock output of channel 17. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK17_N
B1
O
CK18_P
C1
O
LP-HCSL differential clock output of channel 18. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK18_N
D1
O
CK19_P
E1
O
LP-HCSL differential clock output of channel 19. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK19_N
F1
O
MANAGEMENT AND CONTROL
CKPWRGD_PD#
M6
I, PD
Clock Power Good and Power Down multi-function input pin with internal 120-kΩ
pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be
left no connect.
On first high transition, PWRGD samples the latched SADR[1:0] inputs and starts
up device. After PWRGD has been asserted high for the first time, the pin
becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
OE5#
DATA
L8
I, PD
Output enable for channel 5 and Side-Band Interface data multi-function pin with
internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both
modes are unused, the pin can be left no connect.
When pin E2 = LOW, OE5# mode. Output enable for channel 5, active low.
LOW: enable output channel 5.
HIGH: disable output channel 5.
When pin E2 = HIGH, DATA mode. Side-Band Interface data pin.




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