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CDCDB2000 Datasheet(Hoja de datos) 8 Page - Texas Instruments

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No. de Pieza. CDCDB2000
Descripción  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
Descarga  33 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 8 page
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8
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Electrical Characteristics (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Voltage swing includes overshoot.
(2)
Not tested in production. Ensured by design and characterization.
(3)
Measured into DC test load.
(4)
VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is
rising.
(5)
Measured from rising edge of CLK_IN to any CKx output.
IDD
IO supply current per output
All-outputs disabled
20
mA
All-outputs active, 100MHz
200
Power down mode. CKPWRGD_PD# = 0
8
CLOCK INPUT
fIN
Input frequency
50
100
250
MHz
VIN
Input voltage swing
Differential voltage between CLKIN_P and
CLKIN_N(1)
200
2300
mVDiff-
peak
dV/dt
Input voltage edge rate
20% - 80% of input swing
0.7
V/ns
DVCROSS
Total variation of VCROSS
Total variation across VCROSS
140
mV
DCIN
Input duty cycle
40
60
%
CIN
Input capacitance(2)
Differential capacitance between CLKIN_P
and CLKIN_N pins
2.2
pF
CLOCK OUTPUT
fOUT
Output frequency
50
100
250
MHz
COUT
Output capacitance(1)
Differential capacitance between CKx_P
and CKx_N pins
2.2
pF
VOH
Output high voltage
Single-ended(2)(3)
225
270
mV
VOL
Output low voltage
10
150
VCROSS
Crossing point voltage
Input VCROSS varied by 140 mV.
(3) (4)
130
200
DVCROSS
Total variation of VCROSS
Input VCROSS varied by 140 mV. Variation
of VCROSS
(3) (4)
35
Vovs
Overshoot voltage
(3)
VOH+75
Vuds
Undershoot voltage
(3)
VOL–75
ZDIFF
Differential impedance
Measured at VOL/VOH
81
85
89
ohm
ZDIFF_CROS
S
Differential impedance
Measured at VCROSS
68
85
102
tEDGE
Edge rate
Measured at VCROSS
2
20
V/ns
DtEDGE
Edge rate matching
Measured at VCROSS
20
%
tSTABLE
Power good assertion to stable clock
output
CKPWRGD_PD# pin
transistions from 0 to 1, fIN =
100 MHz
Measured
when
PWRGD
reaches
0.2V
1.8
ms
tDRIVE_PD#
Power good assertion to outputs
driven high
CKPWRGD_PD# pin
transistions from 0 to 1, fIN =
100 MHz
Measured
when
PWRGD
reaches
0.2V
300
µs
tOE
Output enable assertion to stable
clock output
OEx# pin transistions from 1 to 0
10
CLKIN
Periods
tOD
Output enable de-assertion to no
clock output
OEx# pin transistions from 0 to 1
10
tPD
Power down assertion to no clock
output
CKPWRGD_PD# pin transistions from 1 to
0
3
tDCD
Duty cycle distortion
Differential; fIN = 100MHz, fin_DC = 50%
–1.0
1.0
%
tDLY
Propagation delay
(5)0.5
3
ns




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