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CDCDB2000 Datasheet(Hoja de datos) 10 Page - Texas Instruments

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No. de Pieza. CDCDB2000
Descripción  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
Descarga  33 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 10 page
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CKx_P
CKPWRGD_PD#
CKx_N
ttSTABLEt
tDRIVE_PD#
ttPDt
CLKIN
VDD/VDD_A
10
CDCDB2000
SNAS787 – NOVEMBER 2019
www.ti.com
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Timing Requirements (continued)
VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise
noted)
MIN
NOM
MAX
UNIT
(1)
TF = (VIHMIN + 0.15) to (VILMAX - 0.15)
(2)
TR = (VILMAX - 0.15) to (VIHMIN + 0.15)
tF
SMBCLK/SMBDAT fall time(1)
300
ns
tR
SMBCLK/SMBDAT rise time(2)
1000
SIDE-BAND INTERFACE TIMING
tPERIOD
Clock period
40
ns
tSETUP
Setup time to clock
25
tDSU
Data set up time
10
tDHOLD
Data hold time
5
tDELAY
Delay time
25
tPDLY
Propagation delay
4
10
CLK
periods
tSLEW
Clock slew rate
20% - 80%
0.2
3
V/ns
Figure 1. Start-Up With CLKIN Timing Diagram




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