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DAC11001A_V01 Datasheet(Hoja de datos) 15 Page - Texas Instruments

No. de Pieza. DAC11001A_V01
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 15 page
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u
OUT
REFPF
REFNF
REFNF
N
CODE
V
(V
V
)
V
2
OUT
DAC
Register
Buffer
Registers
Power On Reset
REFPF
DGND
AVDD
DAC
DVDD
REFNF
REFPS
REFNS
AGND
VSS
IOVDD
RCM
ROFS
RFB
Power
Down Logic
VCC
SCLK
SDIN
SYNC
SDO
LDAC
CLR
ALARM
15
DAC11001A, DAC91001, DAC81001
www.ti.com
SLASEL0 – OCTOBER 2019
Product Folder Links: DAC11001A DAC91001 DAC81001
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Copyright © 2019, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit DAC81001 (DACx1001) are single-channel DACs. The
unbuffered DAC output architecture is based on an R2R ladder that is designed to provide monotonicity over
wide reference and temperature ranges (1-LSB DNL). This architecture provides a very low-noise (7 nV/
√Hz) and
fast-settling (1 µs) output. The DACx1001 also implement a deglitch circuit that enables low, code- and range-
independent symmetrical glitch at the DAC output. This is extremely useful for creating ultra low harmonic
distortion waveform generation.
The DACx1001 requires external reference voltages on REFPF and REFNF pins. The output of the DAC ranges
from VREFNF to VREFPF. See the Recommended Operating Conditions for VREFPF and VREFNF voltage ranges.
The DACx1001 also includes precision matched gain setting pins (ROFS, RCM, and RFB), Using these pins and
an external op amp, the DAC output can be scaled. The DACx1001 incorporate a power-on-reset circuit that
makes sure that the DAC output powers up at zero scale, and remains at zero scale until a valid DAC command
is issued. The DACx1001 use a 4-wire serial interface that operates at clock rates of up to 50 MHz.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Digital-to-Analog Converter Architecture
The DACx1001 provide 20-bit monotonic outputs using an R2R ladder architecture. The DAC output ranges
between VREFNF and VREFPF based on the 20-bit DAC data, as described in Equation 1:
where
CODE is the decimal equivalent of the DAC-DATA loaded to the DAC.
N is the bits of resolution; 20 for DAC1101A, 18 for DAC91001, 16 for DAC81001.
VREFPF, VREFNF is the reference voltage (positive and negative).
(1)




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