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DAC11001A_V01 Datasheet(Hoja de datos) 19 Page - Texas Instruments

No. de Pieza. DAC11001A_V01
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 19 page
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1
SYNC
SCLK
SDIN
SDO
D23 ± D0
2
3
4
5
6
7
8
9
31
32
33
63
64
65
95
96
97
127
128
D30
D29 D28 D27 D26 D25
D31
D24
Device B Command
Device C Command
Device A Command
Device A Command
Device B Command
Device D Command
Device C Command
1
SYNC
SCLK
SDIN
SDO
2
3
4
5
6
7
8
9
31
32
1
2
3
4
5
6
7
8
9
10
31
32
ÂÂÂ
ÂÂÂ
ÂÂÂ
Read Command
Any Command
Read Data
Z-state
D31 D30 D29 D28 D27 D26 D25 D24 D23
D1
D0
D31 D30 D29 D28 D27 D26 D25 D24 D23
D1
D0
D31 D30 D29 D28 D27 D26 D25 D24 D23
D1
D0
D22
1
SYNC
SCLK
SDIN
2
3
4
5
6
7
8
9
31
32
ÂÂÂ
Write Command
D31 D30
D29 D28 D27 D26 D25
D24 D23
D1
D0
19
DAC11001A, DAC91001, DAC81001
www.ti.com
SLASEL0 – OCTOBER 2019
Product Folder Links: DAC11001A DAC91001 DAC81001
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Copyright © 2019, Texas Instruments Incorporated
8.5 Programming
The DACx1001 family of devices is controlled through a flexible four-wire serial interface that is compatible with
serial interfaces used on many microcontrollers and DSP controllers. The interface provides read and write
access to all registers of the DACx1001 devices. Additionally, the interface can be configured to daisy-chain
multiple devices for write operations.
Each serial interface access cycle is exactly 32 bits long, as shown in Figure 5. A frame is initiated by asserting
SYNC pin low. The frame ends when the SYNC pin is deasserted high. The first bit is read/write bit B31. A write
is performed when this bit is set to 0, and a read is performed when this bit is set to 1. The next 7 bits are
address bits B30 to B24. The next 20 bits are data. For all writes, data are clocked on the falling edge of SCLK.
As Figure 6 shows, for read access and daisy-chain operation, the data are clocked out on the SDO terminal on
the rising edge of SCLK.
Figure 5. Serial Interface Write Bus Cycle: Standalone Mode
Figure 6. Serial Interface Read Bus Cycle
8.5.1 Daisy-Chain Operation
For systems that contain several DACx1001 devices, the SDO pin is used to daisy-chain the devices together.
The daisy-chain feature is useful in reducing the number of serial interface lines. The first falling edge on the
SYNC pin starts the operation cycle, as shown in Figure 7. SCLK is continuously applied to the input shift
register while the SYNC pin is kept low. The DAC is updated with the data on rising edge of SYNC pin.
Figure 7. Serial Interface Daisy-Chain Write Cycle
If more than 32 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line.
These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO
output of the first device to the SDI input of the next device in the chain, a multiple-device interface is
constructed. Each device in the system requires 32 clock pulses.




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