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DAC11001A_V01 Datasheet(Hoja de datos) 23 Page - Texas Instruments

No. de Pieza. DAC11001A_V01
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 23 page
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23
DAC11001A, DAC91001, DAC81001
www.ti.com
SLASEL0 – OCTOBER 2019
Product Folder Links: DAC11001A DAC91001 DAC81001
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
8.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h]
Figure 10. CONFIG1 Register Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read/
Write
Address
EN_
TMP_
CAL
0h
TNH_MASK
0h
R/W
W
R/W
W
R/W
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0h
LDAC
MODE
FSDO
ENALMP
DSDO
FSET
VREFVAL
0h
PDN
0h
W
R/W
W
R/W
W
Table 7. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
Read/Write
R/W
N/A
Read when set to 1 or write when set to 0
30:24
Address
W
N/A
02h
23
EN_TMP_CAL
R/W
N/A
Enables and disables the temperature calibration feature
0 : Temperature calibration feature disabled (default)
1 : Temperature calibration feature enabled
22:20
0h
W
N/A
N/A
19-18
TNH_MASK
R/W
0h
Mask track and hold (TNH) circuit. This bit is writable only when FSET = 0
[fast-settling mode] and DIS_TNH = 0 [track-and-hold enabled]
00: TNH masked for code jump > 2^14 (default)
01: TNH masked for code jump > 2^15
10: TNH masked for code jump > 2^13
11: TNH masked for code jump > 2^12
17:15
0h
W
N/A
N/A
14
LDACMODE
R/W
1
Synchronous or asynchronous mode select bit
0 : DAC output updated on SYNC rising edge
1 : DAC updated on LDAC falling edge (default)
13
FSDO
R/W
0h
Enable Fast SDO
0 : Fast SDO disabled (Default)
1 : Fast SDO enabled
12
ENALMP
R/W
0h
Enable ALARM pin to be pulled low, end of temperature calibration cycle
0 : No alarm on the ALARM pin
1 : Indicates end of temperature calibration cycle. ALARM pin pulled low.
11
DSDO
R/W
1h
Enable SDO (for readback and daisy-chain)
1 : SDO enabled (default)
0 : SDO disabled
10
FSET
R/W
1h
Fast-settling vs enhanced THD mode
0 : Fast settling
1 : Enhanced THD (default)
9:6
VREFVAL
R/W
2h
Reference span value bits
0000: Invalid
0001: Invalid
0010: Reference span = 5 V ± 1.25 V (default)
0011: Reference span = 7.5 V ± 1.25 V
0100: Reference span = 10 V ± 1.25 V
0101: Reference span = 12.5 V ± 1.25 V
0110: Reference span = 15 V ± 1.25 V
0111: Reference span = 17.5 V ± 1.25 V
1000: Reference span = 20 V ± 1.25 V
1001: Reference span = 22.5 V ± 1.25 V
1010: Reference span = 25 V ± 1.25 V
1011: Reference span = 27.5 V± 1.25 V
1100: Reference span = 30 V ± 1.25 V
5
0
W
N/A
N/A
4
PDN
R/W
0h
Powers down and power up the DAC
0 : DAC power up (default)
1 : DAC power down
3:0
0000
R/W
N/A
N/A




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