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DAC11001A_V01 Datasheet(Hoja de datos) 29 Page - Texas Instruments

No. de Pieza. DAC11001A_V01
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 29 page
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DAC110 01
SYNC
SDO
SDIN
SCLK
LDAC
CLR
ALA RM
IOVDD
RS
RS
RS
RS
DGND
IOVDD
PROCESS OR
RPULLUP
DGND
IOVDD
SCLK
MOSI
MIS O
CS
INT
GPIO
GPIO
RS
RS
Low-jitte r
LDAC
Sou rce
DAC110 01
SYNC
SDO
SDIN
SCLK
LDAC
CLR
ALA RM
IOVDD
R
S
R
S
R
S
R
S
R
S
DGND
IOVDD
PROCESS OR
R
PUL LU P
DGND
IOVDD
SCLK
MOSI
MIS O
CS
TIMER
GPIO
GPIO
29
DAC11001A, DAC91001, DAC81001
www.ti.com
SLASEL0 – OCTOBER 2019
Product Folder Links: DAC11001A DAC91001 DAC81001
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Copyright © 2019, Texas Instruments Incorporated
9.3 System Examples
This section provides details on the digital interface and the embedded resistor configurations.
9.3.1 Interfacing to a Processor
The DACx1001 family of DACs works with a 4-wire SPI interface. The digital interface of the DACx1001 to a
processor is shown in Figure 19. The DACx1001 has an LDAC input option for synchronous output update. In
ac-signal generation applications, the jitter in the LDAC signal contributes to signal-to-noise ratio (SNR).
Therefore, the LDAC signal must be generated from a low-jitter timer in the processor. The CLR and ALARM
pins are static signals, and therefore can be connected to general-purpose input-output (GPIO) pins on the
processor. All active-low signals (SYNC, LDAC, CLR, and ALARM) must be pulled up to IOVDD using 10-kΩ
resistors. ALARM is an output pin from the DAC, so the corresponding GPIO on the processor must be
configured as an input. Either poll the GPIO, or configured the GPIO as an interrupt to detect any failure alarm
from the DAC. When using a high SCLK frequency, use source termination resistors, as shown in Interfacing to a
Processor. Typically, 33-Ω resistors work on printed circuit boards (PCBs) with a 50-Ω trace impedance.
Figure 19. Interfacing to a Processor
9.3.2 Interfacing to a Low-Jitter LDAC Source
When the processor is not able to provide a low-jitter source for the LDAC signal, an external low-jitter LDAC
source can be used, as shown in Figure 20. The processor can take the LDAC signal as an interrupt and trigger
the SPI frame synchronously.
Figure 20. Interfacing to an External LDAC Source




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