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DAC53401_V01 Datasheet(Hoja de datos) 19 Page - Texas Instruments

No. de Pieza. DAC53401_V01
Descripción  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
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Fabricante  TI1 [Texas Instruments]
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 19 page
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Data output
by transmitter
Data output
by receiver
SCL from
Not acknowledge
Clock pulse for
DAC53401, DAC43401
Product Folder Links: DAC53401 DAC43401
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Copyright © 2019, Texas Instruments Incorporated
8.5 Programming
The DACx3401 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in
the Pin Configuration and Functions section. The I2C bus consists of a data line (SDA) and a clock line (SCL)
with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible
devices connect to the I2C bus through the open drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3401 family operates as a
slave device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives
or transmits data.
Typically, the DACx3401 family operates as a slave receiver. A master device writes to the DACx3401, a slave
receiver. However, if a master device requires the DACx3401 internal register data, the DACx3401 operates as a
slave transmitter. In this case, the master device reads from the DACx3401. According to I2C terminology, read
and write refer to the master device.
The DACx3401 family is a slave and supports the following data transfer modes:
Standard mode (100 kbps)
Fast mode (400 kbps)
Fast+ mode (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to
as F/S-mode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not
output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes. The
DACx3401 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports
the general call reset function. Sending the following sequence initiates a software reset within the device: start
or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the falling edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the
high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of
the ninth clock cycle as shown in Figure 4.
Figure 4. Acknowledge and Not Acknowledge on the I2C Bus

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