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DAC53401_V01 Datasheet(Hoja de datos) 20 Page - Texas Instruments
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SLASES7 – JULY 2019
Product Folder Links: DAC53401 DAC43401
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Copyright © 2019, Texas Instruments Incorporated
8.5.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 5. All I
recognize a start condition.
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in
Figure 6. All devices recognize the address sent by the master and compare the address to the respective
internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling
the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 4. When the master
detects this acknowledge, the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be
generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences
consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high (see Figure 5). This action releases the bus and stops the
communication link with the addressed slave. All I
C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
Figure 5. Start and Stop Conditions
Figure 6. Bit Transfer on the I
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