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DAC53401_V01 Datasheet(Hoja de datos) 21 Page - Texas Instruments

No. de Pieza. DAC53401_V01
Descripción  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 21 page
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1
7
8
9
1
2 - 8
9
S
or
Sr
SDA
SCL
MSB
Address
START or
REPEATED
START
condition
Recognize
START or
REPEATED
START
condition
R/W
ACK
Acknowledgement
signal from Slave
Generate ACKNOWLEDGE
signal
Clock line held low while
interrupts are serviced
Sr
or
P
P
Sr
REPEATED
START or
STOP
condition
Recognize
STOP or
REPEATED
START
condition
ACK
21
DAC53401, DAC43401
www.ti.com
SLASES7 – JULY 2019
Product Folder Links: DAC53401 DAC43401
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
8.5.2 DACx3401 I2C Update Sequence
For a single update, the DACx3401 requires a start condition, a valid I2C address byte, a command byte, and two
data bytes, as listed in Table 10.
Table 10. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
Address Byte
Command byte
Command Byte
Data byte - MSDB Data
Byte (MSDB and LSDB)
Data byte - LSDB Data
Byte (MSDB and LSDB)
DB [32:24]
DB [23:16]
DB [15:8]
DB [7:0]
After each byte is received, the DACx3401 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in Figure 7. These four bytes and acknowledge cycles make up the
36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3401 devices.
Figure 7. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx3401 device. For a data update to occur when
the operating mode is selected by this byte, the DACx3401 device must receive two data bytes: the most
significant data byte (MSDB) and least significant data byte (LSDB). The DACx3401 device performs an update
on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the
fast+ mode (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition is
received, the DACx3401 device releases the I2C bus and awaits a new start condition.
8.5.3 Address Byte
The address byte, as shown in Table 11, is the first byte received following the start condition from the master
device. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently responds to that particular address according to Table 12.
The DACx3401 family supports broadcast addressing, which can be used for synchronously updating or
powering down multiple DACx3401 devices. The DACx3401 family is designed to work with other members of
the family to support multichip synchronous updates. Using the broadcast address, the DACx3401 devices
respond regardless of the states of the address pins. Broadcast is supported only in write mode.




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