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DAC53401_V01 Datasheet(Hoja de datos) 7 Page - Texas Instruments

No. de Pieza. DAC53401_V01
Descripción  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
Descarga  43 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 7 page
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7
DAC53401, DAC43401
www.ti.com
SLASES7 – JULY 2019
Product Folder Links: DAC53401 DAC43401
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Copyright © 2019, Texas Instruments Incorporated
7.6 Timing Requirements: I
2CTM Standard mode
all input signals are specified with tR = tF = 1 ns/V (VIL to VIH) and timed from a voltage level of (VIL + VIH) / 2, 1.8 V ≤ VDD
5.5 V, –40°C
≤ TA ≤ +125°C, Vpull-up = VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull-up = 2.7 or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
NOM
MAX
UNIT
fSCLK
SCL frequency
0.1
MHz
tBUF
Bus free time between stop and start conditions
4.7
µs
tHDSTA
Hold time after repeated start
4
µs
tSUSTA
Repeated start setup time
4.7
µs
tSUSTO
Stop condition setup time
4
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
250
ns
tLOW
SCL clock low period
4700
ns
tHIGH
SCL clock high period
4700
ns
tF
Clock and data fall time
300
ns
tR
Clock and data rise time
1000
ns
7.7 Timing Requirements: I
2CTM Fast mode
all input signals are specified with tR = tF = 1 ns/V (VIL to VIH) and timed from a voltage level of (VIL + VIH) / 2, 1.8 V ≤ VDD
5.5 V, –40°C
≤ TA ≤ +125°C, Vpull-up = VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull-up = 2.7 or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
NOM
MAX
UNIT
fSCLK
SCL frequency
0.4
MHz
tBUF
Bus free time between stop and start conditions
1.3
µs
tHDSTA
Hold time after repeated start
0.6
µs
tSUSTA
Repeated start setup time
0.6
µs
tSUSTO
Stop condition setup time
0.6
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
ns
tF
Clock and data fall time
300
ns
tR
Clock and data rise time
300
ns




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