DAC43401DSGR datasheet(5/43 Pages) TI1

No. de pieza	DAC43401DSGR

Descripción Electrónicos	DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus??Compatible I2C Interface in Tiny 2 횞 2 WSON

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Fabricante Electrónico	TI1 [Texas Instruments]

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DAC53401, DAC43401

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SLASES7 – JULY 2019

Product Folder Links: DAC53401 DAC43401

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(1)

Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for

8-bit resolution. For internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes: 4d to 1016d for 10-bit resolution, 1d to 251d

for 8-bit resolution.

(2)

Specified by design and characterization, not production tested.

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,

DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive

load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

Resolution

DAC53401

10

Bits

DAC43401

8

INL

Relative accuracy(1)

–1

1

LSB

DNL

Differential nonlinearity(1)

–1

1

LSB

Zero code error

Code 0d into DAC

6

12

mV

Internal VREF, gain = 4x, VDD = 5.5 V

12

24

Zero code error temperature

coefficient

±20

µV/°C

Offset error(1)

–0.5

0.25

0.5

%FSR

Offset error temperature

coefficient(1)

±0.0003

%FSR/°C

Gain error(1)

–0.5

0.25

0.5

%FSR

Gain error temperature

coefficient(1)

±0.0008

%FSR/°C

Full scale error

2.7 V

≤ VDD ≤ 5.5 V, code 1023d into DAC,

no headroom

–0.5

0.25

0.5

%FSR

1.8 V

≤ VDD ≤ 2.7 V, code 1023d into DAC,

no headroom

–1

0.5

1

Full scale error temperature

coefficient

±0.0008

%FSR/°C

OUTPUT CHARACTERISTICS

Output voltage

Reference tied to VDD

0

5.5

V

CL

Capacitive load(2)

RL = Infinite, phase margin = 30°

1

nF

RL = 5 kΩ, phase margin = 30°

2

Load regulation

DAC at midscale, –10 mA

≤ IOUT ≤ 10 mA,

VDD = 5.5 V

1.5

mV/mA

Short circuit current

VDD = 1.8 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD

10

mA

VDD = 2.7 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD

25

VDD = 5.5 V, full-scale output shorted to AGND or

zero-scale output shorted to VDD

50

Output voltage headroom

To VDD (DAC output unloaded, internal reference =

1.21 V), VDD ≥ 1.21 ☓ gain + 0.2 V

0.2

V

To VDD

(DAC output unloaded, reference tied to VDD)

0.8

%FSR

To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA

at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC

code = full scale

10

VOUT dc output impedance

DAC output enabled and DAC code = midscale

0.25

Ω

DAC output enabled and DAC code = 4d

0.25

DAC output enabled and DAC code = 1016d

0.26

VFB dc output impedance

DAC output enabled

160

200

240

kΩ

DAC output enabled, internal VREF, gain = 4x

192

240

288

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