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DLPC900_V01 Datasheet(Hoja de datos) 14 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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14
DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Refer to I/O Type and Subscript Definition (Table 1).
(2)
This signal does not apply to the slave controller in a two controller system configuration. On the slave controller, this pin is reserved
and should be left unconnected. Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description
between a one controller and a two controller configuration.
Clock and PLL Support Pin Functions
PIN
I/O
POWER
I/O TYPE
(1)
CLK SYSTEM
DESCRIPTION
NAME
NUMBER
MOSC
M26
VDD33
I10
N/A
System clock oscillator input (3.3-V LVTTL). MOSC must be
stable a maximum of 25 ms after POSENSE transitions from
low to high.
MOSCN
N26
VDD33
O10
N/A
MOSC crystal return.
OCLKA (2)
AF6
VDD33
O5
Async
General-purpose output clock A. The frequency is software
programmable. Power-up default is 787 kHz and the output
frequency is maintained through all operations, except
power loss and reset.
(1)
All JTAG signals are LVTTL compatible.
(2)
Refer to I/O Type and Subscript Definition (Table 1).
Board-Level Test and Debug Pin Functions (1)
PIN
I/O
POWER
I/O TYPE
(2)
CLK
SYSTEM
DESCRIPTION
NAME
NUMBER
TDI
N25
VDD33
I4
U
TCK
JTAG serial data in. Used in both Boundary Scan and ICE
modes.
TCK
N24
VDD33
I4
D
N/A
JTAG serial data clock. Used in both Boundary Scan and ICE
modes.
TMS1
P25
VDD33
I4
U
TCK
JTAG test mode select. Used in Boundary Scan mode.
TMS2
P26
VDD33
I4
U
TCK
JTAG-ICE test mode select. Used in ICE mode.
TDO1
N23
VDD33
O5
TCK
JTAG serial data out. Used in Boundary Scan mode.
TDO2
N22
VDD33
O5
TCK
JTAG-ICE serial data out. Used in ICE mode.
TRSTZ
M23
VDD33
I4
H
U
Async
JTAG Reset. Used in both Boundary Scan and ICE modes.
This pin should be pulled high (or left unconnected) when the
JTAG interface is in use for boundary scan or debug.
Connect this to ground otherwise. Failure to tie this pin low
during normal operation will cause startup and initialization
problems.
RTCK
E4
VDD33
O2
N/A
JTAG return clock. Used in ICE mode.
ICTSEN
M24
VDD33
I4
H
D
Async
IC tri-state enable (active high). Asserting high will tri-state all
outputs except the JTAG interface. Requires an external
4.7 kΩ pulldown resistor.
(1)
Refer to I/O Type and Subscript Definition (Table 1).
Device Test Pin Functions
PIN
I/O
POWER
I/O TYPE
(1)
CLK
SYSTEM
DESCRIPTION
NAME
NUMBER
HW_TEST_EN
M25
VDD33
I4
H
D
N/A
Device manufacturing test enable. This signal must be
connected to an external ground for normal operation.




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