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DLPC900_V01 Datasheet(Hoja de datos) 3 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
Changes from Revision B (September 2016) to Revision C
Page
Updated description of POSENSE and PWRGOOD.............................................................................................................. 5
Changed Reset Timing Requirements to Power-Up and Power-Down Timing Requirements. ........................................... 27
Added power-up and power-down requirements for revision "B" DMDs.............................................................................. 27
Updated the description of Power-On Sense (POSENSE) Support and added cross-reference to Power-Up and
Power-Down Timing Requirements. ..................................................................................................................................... 61
Updated the description of Power Good (PWRGOOD) Support and added cross-reference to Power-Up and Power-
Down Timing Requirements. ................................................................................................................................................ 61
Changes from Revision A (August 2015) to Revision B
Page
Changed "DLP9500" to "DLP9000" ........................................................................................................................................ 1
Changed "247 Hz" to "1031 Hz"; added "External Input up to 360 Hz" ................................................................................. 1
Changed number of patterns for 48Mbit External Flash......................................................................................................... 1
Added "or 50 8-Bit Grayscale Patterns" ................................................................................................................................. 1
Added Memory Design Considerations section .................................................................................................................. 42
Added "(pre-stored pattern mode, pattern on-the-fly mode, or video pattern mode)," ......................................................... 48
Added "pattern on-the-fly mode." ......................................................................................................................................... 48
Changed to "In video pattern mode, pre-stored pattern mode, and pattern on-the-fly mode," ............................................ 48
Added "For faster 8-bit pattern speeds, . . ." ........................................................................................................................ 49
Added link to "DLP6500 & 9000 EVM User's Guide" ........................................................................................................... 49
Added row to "Minimum Exposure in Any Pattern Mode" .................................................................................................... 49
Changes from Original (October 2014) to Revision A
Page
Changed phrasing of pattern speed features ......................................................................................................................... 1
Corrected the width of the input pixel ports to 24-bits ............................................................................................................ 1
Added I/O Type and Subscript Definition table ...................................................................................................................... 5
Corrected maximum port width of Ports 1 and 2 in table note ............................................................................................. 11
Updated ESD Ratings table title and value column ............................................................................................................. 22
ESD sensitivity machine model was removed...................................................................................................................... 22
Added note to clarify that Ports 1 and 2 are used as 24-bit buses ...................................................................................... 32
Changed section title to correct bus size to 48-bits.............................................................................................................. 33
Removed references to 30-bit RGB video............................................................................................................................ 39
Corrected minor typos .......................................................................................................................................................... 48
Corrected video pattern mode timing diagram and description............................................................................................ 48
Corrected pre-stored pattern mode timing diagram and description .................................................................................... 48
Corrected pre-stored pattern mode 3 pattern example diagram and description................................................................. 48
Removed Allowed Pattern Combinations table .................................................................................................................... 49
Added Minimum Exposure in Any Pattern Mode table......................................................................................................... 49
Added Minimum Exposures for Number of Active DMD Blocks table.................................................................................. 50
Updated Boot Flash Memory Layout image to reflect firmware version 2.0 ........................................................................ 52
Corrected video data interface size to 24-bits ...................................................................................................................... 53
Corrected video mode port maximum size to 24 bits ........................................................................................................... 54
Corrected P1 and P2 signal description regarding 24-bit bus width .................................................................................... 54
Corrected spacing and formatting ........................................................................................................................................ 62
Corrected minor typo ............................................................................................................................................................ 71




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