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DLPC900_V01 Datasheet(Hoja de datos) 34 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 34 page
background image
tc
tw(H)
tsu
P_CLKx or
Px_CLK
(input)
Valid
Px_Data and
Px_Control
(inputs)
50%
20%
50%
50%
tw(L)
tt
th
80%
34
DLPC900
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
www.ti.com
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Values chosen for front and back porches must meet the timing requirements in Source Input Blanking Requirements.
Figure 8. Input Port 1 and 2 Interface
6.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
When operating in two pixels per clock mode, the pixel clock must be maintained below 141 MHz. A typical video source
requiring two pixels per clock is shown in the following table and must have reduced blanking to stay below the maximum
pixel clock.
SOURCE
RATE (Hz)
TOTAL PIXELS PER LINE (1)
TOTAL LINES PER FRAME (1)
PIXEL CLOCK
ACHIEVED (MHz)
1080p
120
2060
1120
138.4
(1)
The SSP is configured into four different modes of operation by the controller firmware. These modes are shown in Table 3, Figure 10,
and Figure 11.
(2)
Modes 0 and 3
(3)
Modes 1 and 2
6.13 SSP Switching Characteristics
Switching characteristics over recommended operating conditions, CL (min timing) = 5 pF, CL (max timing) = 50 pF (unless
otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
MIN
MAX
UNIT
ƒclock
Clock frequency, SSPx_CLK
N/A
SSPx_CLK
73.00
25000
kHz
tc
Cycle time, SSPx_CLK
N/A
SSPx_CLK
0.040
13.6
µs
tw(H)
Pulse duration, high
50% to 50% reference points (signal)
N/A
SSPx_CLK
40%
tw(L)
Pulse duration, low
50% to 50% reference points (signal)
N/A
SSPx_CLK
40%
SSP MASTER
tpd
Output propagation, clock to Q,
SSPx_DO
SSPx_CLK
(1) (2)
SSPx_DO (1) (2)
–5
5
ns
SSPx_CLK
(1) (3)
SSPx_DO (1) (3)
–5
5
ns
SSP SLAVE
tpd
Output propagation, clock to Q,
SSPx_DO
SSPx_CLK
(1) (2)
SSPx_DO (1) (2)
0
34
ns
SSPx_CLK
(1) (3)
SSPx_DO (1) (3)
0
34
ns
Table 3. SSP Clock Operational Modes
SPI CLOCKING
MODE
SPI CLOCK
POLARITY (CPOL)
SPI CLOCK PHASE
(CPHA)
0
0
0
1
0
1
2
1
0
3
1
1




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