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DLPC900_V01 Datasheet(Hoja de datos) 37 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 37 page
background image
tc
tw(H)
DCKA
DCKB
(output)
Valid
SCA, DDA(15:0)
SCB, DDB(15:0)
(outputs)
50%
20%
50%
50%
tw(L)
tt
th
Valid
tsu
Valid
th
tsu
80%
37
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
The minimum cycle time (tc) for DCK_A and DCK_B includes 1.0% spread spectrum modulation.
(2)
The DMD LVDS interface uses a double data rate (DDR) clock, thus both rising and falling edges of DCK_A and DCK_B are used to
clock data into the DMD. As a result, the minimum tw(H) and tw(L) parameters determine the worse-case DDR clock cycle time.
(3)
Output setup and hold times for DMD clock frequencies below the maximum can be calculated as follows:
tosuclock) = tosumax) + 250000 × (1 / ƒclock – 1 / 400) and tohclock) = tohmax) + 250000 × (1 / ƒclock – 1 / 400) where ƒclock is in MHz.
(4)
The DLPC900 is a Full-Bus DMD signaling interface. Figure 18 shows the controller connections for this configuration.
(5)
The pulse duration minimum for any clock rate can be calculated using the following formulas.
(a) Pulse duration minimum when using spread spectrum
(a) Duty cycle % = 49.06 – [0.01335 × clock frequency (MHz)]
(b) Minimum pulse duration = 1 / clock frequency × DC%
(a) Example: At 400 MHz: DC% = 49.06 – [0.01335 × 400] = 43.72%
(b) MPW = 1 / 400 MHz × 0.4372 = 1093.0 ps
(b) Pulse duration minimum when not using spread spectrum
(a) Duty cycle % = 49.00 – [0.01055 × clock frequency (MHz)]
(b) Minimum pulse duration = 1 / clock frequency × DC%
(a) Example: At 400 MHz: DC% = 49.00 – [0.01055 × 400] = 44.78%
(b) MPW = 1 / 400 MHz × 0.448 = 1119.5 ps
(6)
A duty cycle specification is not provided because the key limiting factor to clock frequency is the minimum pulse duration (that is, if the
other half of the clock period is larger than the minimum, it is not limiting the clock frequency).
6.15 DMD LVDS Interface Switching Characteristics
Switching characteristics over recommended operating conditions
(1) (2) (3) (4) (5) (6)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
MIN
MAX
UNIT
ƒclock
Clock frequency, DCK_A
N/A
DCK_A
100
400
MHz
tc
Cycle time, DCK_A1
N/A
DCK_A
2475.3
ps
tw(H)
Pulse duration, high 5 (50% to 50% reference
points)
N/A
DCK_A
1093
ps
tw(L)
Pulse duration, low 5 (50% to 50% reference
points)
N/A
DCK_A
1093
ps
tt
Transition time, tt = tƒ / tr (20% to 80% reference
points)
N/A
DCK_A
100
400
ps
tosu
Output setup time at max clock rate3
DCK_A
↑↓
SCA, DDA(15:0)
438
ps
toh
Output hold time at max clock rate3
DCK_A
↑↓
SCA, DDA(15:0)
438
ps
ƒclock
Clock frequency, DCK_B
N/A
DCK_B
100
400
MHz
tc
Cycle time, DCK_B1
N/A
DCK_B
2475.3
ps
tw(H)
Pulse duration, high 5 (50% to 50% reference
points)
N/A
DCK_B
1093
ps
tw(L)
Pulse duration, low 5 (50% to 50% reference
points)
N/A
DCK_B
1093
ps
tt
Transition time, tt = tƒ / tr (20% to 80% reference
points)
N/A
DCK_B
100
400
ps
tosu
Output setup time at max clock rate3
DCK_B
↑↓
SCB, DDB(15:0)
438
ps
toh
Output hold time at max clock rate3
DCK_B
↑↓
SCB, DDB(15:0)
438
ps
tsk
Output skew, channel A to channel B
DCK_A
DCK_B
250
ps
Figure 13. DMD LVDS Interface




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