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DLPC900_V01 Datasheet(Hoja de datos) 41 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 41 page
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Full-Bus
A Port Normal
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DLPC900
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DLPC900
41
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Feature Description (continued)
Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on
or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With binary pulse-
width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on.
For a 24-bit RGB frame image inputted to the DLPC900 controller, the DLPC900 controller creates 24 bit-planes,
stores them in internal embedded DRAM, and sends them to the DMD, one bit-plane at a time. The bit weight
controls the amount of time the mirror is on. To improve image quality in video frames, these bit-planes, time
slots, and color frames are shuffled and interleaved within the pixel processing functions of the DLPC900
controller.
7.3.1 DMD Configurations
Figure 18 shows the controller connections for full-bus normal or swapped. Refer to the Firmware section of the
DLP® LightCrafter™ 6500 and 9000 Evaluation Module (EVM) User's Guide (DLPU028) for details on how to
select the bus swap settings to match the board layout connections.
Figure 18. Controller to DMD Full-Bus Connections
7.3.2 Video Timing Input Blanking Specification
The DLPC900 controller requires a minimum horizontal and vertical blanking for both Port 1 and Port 2 as shown
in Source Input Blanking Requirements. These parameters indicate the time allocated to retrace the signal at the
end of each line and field of a display. Refer to DEFINITIONS - Video Timing Parameters.
7.3.3 Board-Level Test Support
The In-Circuit Tri-State Enable signal (ICTSEN) is a board-level test control signal. By driving ICTSEN to a logic
high state, all controller outputs (except TDO1 and TDO2) will be configured as tri-state outputs.
The DLPC900 also provides JTAG boundary scan support on all I/O except non-digital I/O and a few special
signals. Table 4 lists these exceptions.




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