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DLPC900_V01 Datasheet(Hoja de datos) 43 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 43 page
background image
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Boot Flash
CS1
0xF8000000
0xF8FFFFFF
0xF8F00000
RESERVED
CS0
Bootloader
Main Application
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storage
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storage
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0xFAFFFFFF
CS2
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storage
43
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
7.3.5 Memory Design Considerations
7.3.5.1 Flash Memory Optimization
The DLPC900 memory configuration can be optimized for different applications. The operating mode chosen and
the application implementation will determine how much optimization can be performed.
7.3.5.2 Operating Modes
The DLPC900 firmware offers four operating modes which can be selected when designing a product for a
particular application.
1. Video Mode: streamed over parallel RGB interface.
2. Video Pattern Mode: streamed over parallel RGB interface.
3. Pre-Stored Pattern Mode: patterns loaded from stored memory.
4. Pattern On-The-Fly Mode: patterns loaded over USB or I2C interface.
Depending on the application design requirements, the memory required for each operating mode may be
optimized for both performance and cost. This includes reducing the number of flash memory components, which
reduces PCB size and lowers overall product cost. In addition, having fewer components reduces the power
supply requirements hence lowering total power consumption.
7.3.5.3 DLPC900 Memory Space
The memory space of the DLPC900 consists of three chip-selects.
1. CS0
2. CS1 - Power-up boot chip select
3. CS2
The DLPC900 is capable of accessing up to 16 Mbit of memory on each chip-select for a total of 48 Mbit. CS1
contains the firmware, and it is the power-up boot chip-select.
The memory space shown in Figure 20 is used on the DLP6500 and DLP9000 EVMs from TI. Although the chip-
selects are numbered 0, 1, and 2, the way the DLPC900 accesses the memory is not in this order. Figure 20
shows how the DLPC900 accesses the memory when memory is present on all three chip-selects. Notice that
the boot flash is located on chip-select CS1.
Figure 20. DLPC900 Memory Space
During the power-up initialization, the DLPC900 firmware performs a query on each chip-select to determine
whether there is memory present. If there is no memory present on CS1, then the DLPC900 will not boot up.
Therefore, flash memory and the firmware must exist on CS1.




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