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DLPC900_V01 Datasheet(Hoja de datos) 55 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
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Copyright © 2014–2019, Texas Instruments Incorporated
(1)
The A, B, and C input data channels of Port 1 and 2 can be internally swapped for optimum board layout. Refer to the DLPC900
Programmers Guide for details on how to configuring the port settings to match the board layout connections.
8.2.1.2.1.2
Input Data Interfaces
The data interface has a Parallel RGB input port and has a nominal I/O voltage of 3.3 V. Maximum and minimum
input timing specifications for both components are provided in the Interface Timing Requirements. Each parallel
RGB port can support up to 24 bits in Video Mode.
Table 8. Active Signals – Data Interface
SIGNAL NAME
DESCRIPTION
RGB Parallel Interface Port 1
P1_(A, B, C)_[2:9] (1)
24-bit data inputs, 8 bits for each of the red, green, and blue channels. When interfacing to a system with 8-bits
per color or less, connect the bus of the red, green, and blue channels to the upper bits of the DLPC900 10-bit
bus.
P_CLK1
Pixel clock; all input signals on data interface are synchronized with this clock.
P1_VSYNC
Vertical sync
P1_HSYNC
Horizontal sync
P_DATAEN1
Input data valid
RGB Parallel Interface Port 2
P2_(A, B, C)_[0:9] (1)
24-bit data inputs, 8 bits for each of the red, green, and blue channels. When interfacing to a system with 8-bits
per color or less, connect the bus of the red, green, and blue channels to the upper bits of the DLPC900 10-bit
bus.
P_CLK2
Pixel clock; all input signals on data interface are synchronized with this clock.
P2_VSYNC
Vertical sync
P2_HSYNC
Horizontal sync
P_DATAEN2
Input data valid
Optional Pixel Clock 3
P_CLK3
Pixel clock; all input signals on data interface are synchronized with this clock.




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