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DLPC900_V01 Datasheet(Hoja de datos) 57 Page - Texas Instruments

No. de Pieza. DLPC900_V01
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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 57 page
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CSZ
WEZ
OEZ
WD31:16
RD15:0
RD31:16
WD15:0
TACC
TWP
TCS
TCH
DATA
WRITE
READ
57
DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
(1)
Assumes a maximum single direction trace length of 75 mm.
(2)
In some flash device data sheets, the read access time may also be represented as TOE, TE, TRC, or TCE. Use the largest of these
values to calculate the wait-states for the read access time.
(3)
For each parameter.
8.2.1.2.1.4.2
Program Memory Flash Interface
The DLPC900 provides three external program memory chip selects for standard NOR-type flash:
PM_CSZ_0 – flash device (
≤ 128 Mbit)
PM_CSZ_1 – dedicated CS for boot flash device (
≤ 128 Mbit). Refer to the Figure 32 for the memory layout of
the boot flash.
PM_CSZ_2 – flash device (
≤ 128 Mbit)
Flash access timing is programmable up to 19 wait-states. Table 11 contains the formulas to calculate the
required wait-states for each of the parameters shown in Figure 33 for a typical flash device. Refer to the
DLPC900 Programmers Guide for details on how to set new wait-state values.
Table 11. Flash Wait-States
PARAMETER
FORMULA (1)
DEFAULT
TCS (CSZ low to WEZ low )
= Roundup((TCS+ 5 ns) / 6.7 ns)
2
TWP (WEZ low to WEZ high)
= Roundup((TWP+ 5 ns) / 6.7 ns)
11
TCH (WEZ high to CSZ high )
= Roundup((TCH+ 5 ns) / 6.7 ns)
2
TACC (CSZ low to Output Valid )
(2)
= Roundup((TACC+ 5 ns) / 6.7 ns)
19
Maximum supported wait-states
19 (120ns) (3)
Figure 33. Flash Interface Timing Diagram




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